Stratix® IV GX Transceivers: PCS

Stratix IV GX FPGAs include specific digital functionality to deliver physical coding sublayer (PCS) compliance for a number of key protocols used in backplane, line card, and chip-to-chip applications. These digital blocks are optimized for enhanced protocol support, reducing the amount of resources required in the device to implement the physical layer of the protocol while maintaining a low-power solution. The blocks, when combined with specific intellectual property (IP) and reference designs, can provide a complete protocol solution, both simplifying potentially complex designs and reducing project risk. Table 1 shows the key protocols supported by Stratix IV GX FPGAs.

Table 1. Stratix IV GX Protocol Support

Protocol

Data Rate

Complete Solution

PCI Express* Gen1

2.5 Gbps

IP

PCI Express Gen2

5.0 Gbps

IP

Serial RapidIO*

1.25, 2.5, 3.125 Gbps

IP

SerialLite II

622 Mbps–6.375 Gbps

IP

OIF CEI-6G

4.976 Gbps–6.375 Gbps

-

10-Gigabit Ethernet XAUI

3.125 Gbps

IP

HiGig

3.75 Gbps

IP

GPON

1.244 Gbps upstream, 2.488 Gbps downstream

-

SFI-5

2.488 Gbps–3.125 Gbps

-

Gigabit Ethernet (GbE)

1.25 Gbps

IP

SDH/SONET OC-12

622 Mbps

-

SDH/SONET OC-48

2.488 Gbps

-

CPRI

0.6144, 1.288, 2.4576, 3.072 Gbps

IP

Fibre Channel

1.0625, 2.125, 4.25, 8.5 Gbps

-

HyperTransport*

2.4, 2.8, 3.2 Gbps

-

SD-SDI

270 Mbps1

IP

HD-SDI

1.485 Gbps

IP

3G-SDI

2.97 Gbps

IP

Table 2. PCS Implementation by Protocol (8B/10B Encoding)

Required PCS Functions

PCI Express
(Gen1)

PCI Express
(Gen2)

GbE

XAUI

Serial RapidIO®

SerialLite II

Data Rates (Gbps)

2.5

5.0

1.25

3.125

3.125

0.622–6.375

Channel Bonding

1, 4, 8

1, 4, 8

1

4

1, 4

Up to x16

Possible Reference Clock Values (MHz)

100

100

125

156.25

156.25

62.2–622.08

FPGA Bus Width (Bits Per Channel)

8 or 164

164

8

16

16

8, 16, 32

Dedicated Sync State Machine

-

-

Word Align

Rate Match

-

Byte Serialize/Deserialize

-

Phase Compensation FIFO Buffer

Byte Reordering

-

-

-

-

-

-

Single Bit Slip

-

-

-

-

-

Special Interface

PIPE-1.0

PIPE-2.0

GMII Like2

XGMII Like3

-

-

Table 3. PCS Implementation by Protocol (Scrambled Encoding)

Required PCS Functions

CEI-6G

SDH/SONET

Scrambled Backplane

SD-SDI

HD-SDI

3G-SDI

Data Rates (Gbps)

6.375

0.622

2.488

0.2701

1.485

2.97

Channel Bonding

1

1

1

1

1

1

Possible Reference Clock Values (MHz)

155.52– 622.08

62.2, 311.04

77.76, 155.52, 311.04, 622.08

67.5

74.25

74.25

FPGA Bus Width (Bits Per Channel)

32

8

16

10

10

10

Word Align

-

-

-

-

Rate Match

-

-

-

-

-

-

Byte Serialize/Deserialize

-

-

-

-

Phase Compensation FIFO Buffer

Byte Reordering

-

-

-

-

-

Single Bit Slip

-

-

Notes to Tables 2 and 3:
  1. Data rate achieved by oversampling.
  2. GMII support for Gigabit Ethernet only.
  3. XGMII has SDR instead of DDR interface.
  4. Hard IP is not used. When it is used, the PCS to hard IP interface is 8 bits wide for both Gen1 and Gen2.

Each block within the transceiver is highly configurable to support both industry standard and customer proprietary protocols. Transceiver implementation is simplified within the Intel® Quartus® Prime development tool. The tool automatically configures the transceiver PCS block to support the selected protocol, speeding up implementation and reducing design risk. The Intel Quartus Prime software also provides basic configuration modes for proprietary and non-standard protocols.

Built-In Self Test (BIST)

The BIST provides a powerful set of diagnostic capabilities to the transceiver. It includes a pattern generator and checker for pseudo-random binary sequence (PRBS) and others. The BIST also features four loopback configurations that can be used for system diagnostics, allowing interrogation of the physical media attachment (PMA), the PCS, or both the PMA and PCS layers of the transceiver into the FPGA.