Stratix® IV FPGA Core Fabric Architecture

The core fabric of Stratix IV FPGAs is built from innovative logic units known as adaptive logic modules (ALMs). The ALMs are routed with the MultiTrack interconnect architecture, enabling Stratix IV FPGAs to implement high-speed logic, arithmetic, and register functions.

Stratix IV FPGAs carry forward the validated advantages of the innovative ALM logic structure as demonstrated by Stratix® III FPGAs on OpenCore* designs. The ALMs are fully integrated in Intel® Quartus® Prime software to easily deliver the highest performance, highest logic utilization, and lowest compile times.

Adaptive Logic Module

The key to high-performance Stratix IV FPGAs is the area-efficient ALM. It has 8 inputs with a fracturable look-up table (LUT) that can be divided into two adaptive LUTs (ALUTs) using Intel® FPGA's patented LUT technology. Each ALM is capable of:

  • A full 6-input LUT or select 7-input LUT
  • Two independent outputs of multiple combinations of smaller LUT sizes for efficient logic packing
  • Implementing complex logic-arithmetic functions without additional resources

See Figure 1 for the ALM structure, and Table 1 for more detailed information on the features available.

Figure 1. Stratix IV FPGA ALM

Table 1. Stratix IV FPGA ALM Features and Advantages

Available Resources per ALM Advantages
8-Input Fracturable LUT
  • Can implement any 6-input logic function and certain 7-input functions and be fractured into independent smaller LUTs, such as two independent 4-input LUTs
  • Intel® Quartus® Prime software design suite integrates this fracturability and optimizes it for performance, efficiency, power, and area (more logic capacity and less wasted logic)
Two Embedded Adders
  • Allows for two two-bit additions or two three-bit additions without any additional resources
  • Operands can be generated from the same ALM and do not require any additional logic
Two Registers
  • Optimal register-to-logic ratio to ensure device is not register-limited
  • Abundance in registers for register-rich applications or pipeline designs for performance
Two Outputs
  • Inputs of a single ALM can be divided between the two output functions, allowing wide input functions to run fast and narrow input functions to efficiently use remaining resources
MLAB
  • Stratix IV FPGA core is a second variation of the logic array block (LAB), known as the MLAB, that can be used as a regular ALM or configured as simple dual-port SRAM blocks
  • Part of the TriMatrix memory technology, MLABs can be configured as 64 x 10 or 32 x 20 simple dual-port SRAM blocks. The MLABs are optimized to implement filter delay lines, small FIFO buffers, and shift registers with maximum performance of 600-MHz clock speeds

For more information, refer to the Logic Array Blocks & Adaptive Logic Modules (PDF) chapter of the Stratix IV Device Handbook.

The MultiTrack Interconnect

Stratix IV FPGAs leverage the MultiTrack interconnect technology. This technology consists of continuous, performance-optimized routing lines of different lengths used for communication within and between distinct design blocks.

The MultiTrack interconnect technology, shown in Figure 2, is used in Intel® FPGA's Stratix FPGA series to:

  • Provide the industry's best connectivity with up to five times the logic in a single hop (compared to the competition)
  • Provide more accessibility to any surrounding LAB with much fewer connections, thus improving performance and reducing power
  • Avoid area congestion to provide better logic packing

Figure 2. Stratix FPGA Series MultiTrack Interconnect Connectivity

Advantages of Stratix IV FPGA Architecture

The fracturable LUT, two full adders, two registers, and additional logic enhancements that enable the ALM to be partitioned into two independent LUTs for maximizing efficiency make Stratix IV FPGAs the fastest and biggest 40-nm FPGAs—with no wasted logic. Stratix IV devices are:

  • 35 percent faster and can effectively pack 80 percent more logic compared to the nearest competing logic cell, thereby cutting costs by packing more logic in a smaller, less expensive device
  • Fully integrated in Intel Quartus Prime software to optimally utilize the 8-input fracturable LUT in the ALM and the MultiTrack routing interconnect architecture, and improve productivity by easily and reliably meeting timing closure