MAX® V devices are ideal for general-purpose and power- and space-constrained designs in many market segments, including wireline, wireless, industrial, consumer, computer and storage, broadcast, and military. MAX® V CPLDs are used for a wide variety of applications previously implemented in older generation ASICs, ASSPs, FPGAs, and discrete logic devices.
|Cost optimized||Manufactured using a mature, long-life cycle, low-cost 0.18-µm fab process combined with the latest low-cost packaging technologies.|
|Low power||Up to 50% lower total power compared to equivalent density competitive CPLDs, generating less heat and saving battery power.|
|Internal oscillator||Replaces an external discrete timing devices for use as a simple clocking source, saving BOM costs.|
|Fast power-on and reset||Power on and reset quickly (500 µs or less), ideal for power management, power sequencing, and monitoring of other devices on the PCB.|
|Realtime in-system programmability (ISP)||Allow you to update a second configuration image while the CPLD is in operation.|
|I/O capabilities||I/Os are hot-socket compliant and support LVTTL, LVCMOS, PCITM, and LVDS output interface standards, along with other bus-friendly options (e.g. output enable per pin, Schmitt triggers, slew rate control, and others).|
|Green packages||All packages are available in restriction of hazardeous substances (RoHS)-compliant variants, meeting the "low-halogen" requirements per JEDEC document JED 709 (draft). Selected packages are available in leaded variants.|
|Parallel Flash Loader||The on-chip JTAG block can configure external non-JTAG-compliant devices, such as discrete flash memory devices, using the Parallel Flash Loader IP Megafunction.|
Leveraging the successful MAX® II architecture, MAX® V devices combine instant-on, non-volatile CPLD characteristics with advanced features typically found in FPGAs, such as phase-locked loops (PLLs), on-chip memory, and internal oscillators.
MAX® V CPLDs are built using a low-cost fab process combined with a selection of popular, low-cost packages. A pad-limited, staggered I/O pad arrangement results in a small die size, as well as a low-cost-per-I/O pin.
The groundbreaking MAX® V CPLD architecture (Figure 1) includes an array of logic elements (LEs grouped in logic array blocks (LABs)), memory resources (non-volatile flash and LE RAM), digital PLLs, global signals (clocks or control signals), and a generous amount of user I/Os. The MultiTrack interconnect is designed to maximize performance and minimize power by using the most efficient, direct connection from input to logic to output. Find more details about the MAX® V architecture in the MAX® V Device Family Data Sheet (PDF).
To simplify the design optimization process, the MAX® V CPLD architecture and Quartus® Prime software fitting algorithms were refined in concert to optimize tPD, tCO, tSU, and fMAX performance with pins locked down. As design functionality changes, Quartus Prime software enhances the ability to meet or exceed performance requirements using locked pin assignments and a push-button compilation flow. All MAX® V CPLDs are supported by the free Quartus® Prime Lite Edition software.
The MAX® V CPLD architecture supports MultiVolt I/O functionality, allowing different I/O banks to operate with different I/O voltages to seamlessly connect to other devices. The device core is powered by a single 1.8-V external supply (VCCINT), providing CPLD functionality with low dynamic and stand-by power.
The smaller density products have two I/O banks, while the larger density products have four I/O banks. Each bank can be supplied with an independent VCCIOreference voltage.