MAX® II CPLD Features

The MAX® II CPLD architecture has two unique features not found in other CPLD architectures: an internal oscillator and 8 Kbits of non-volatile user flash memory.

Oscillator

User Flash Memory Block and Oscillator

The internal oscillator is a 4.4-MHz (typical output) clock source and resides inside the user flash memory block. Not only does the internal oscillator reduce component count, it can also be used to reduce system power. For example, many industrial and consumer applications, such as portable media players, do not require the CPLD to be powered on all the time. In these applications, it is preferred to have a design in which the CPLD remains off most of the time and only powers on when needed. Intel® MAX II CPLDs are well suited for such applications because:

  • The internal oscillator can be used to automatically turn the device on and off, with no system intervention.
  • When the CPLD is off, the only current consumption is the leakage current due to active inputs (IDK). This current draw is negligible (10 µA), compared to traditional macrocell-based CPLDs, which draw greater than a milliamp.
  • Robust power sequencing allows MAX II CPLDs to power on and off, without adversely affecting the system.

You can find technical information about the oscillator in the Using User Flash Memory in MAX II Devices (PDF) chapter of the MAX II Device Handbook and the altufm_osc megafunction available within the Quartus® II software.

User Flash Memory

The user flash memory is an 8-Kbit user-accessible and programmable block of non-volatile flash memory that stores user-defined data, such as a serial EEPROM. The user flash memory block is accessible by any logic element (LE) within the MAX II CPLD. The user flash memory block offers the following features:

  • Interface to the CPLDs logic array or JTAG circuit
  • Non-volatile storage, 16-bit wide and 8,192 total bits
  • Partitioned as two sectors for independent sector erase, reads, or writes
  • Built-in oscillator that optionally drives the CPLD logic array
  • Optional auto-increment addressing
  • Serial interface to logic array, programmable with a Quartus II automated GUI. Several industry standard protocol options are available:
    • I2C
    • SPI
    • Parallel
    • None (defaults to Intel Serial Interface)

Commonly used applications include using the user flash memory to store the following information: encryption keys, PCB serialization numbers, firmware revision numbers, or initialization code to boot ASICs, ASSPs, analog components, microprocessors, or microcontrollers.

 

You can find technical information about the user flash memory in the Using User Flash Memory in MAX II Devices (PDF) chapter of the MAX II Device Handbook. The user flash memory interfaces with the JTAG circuitry and with the core logic, giving you the flexibility to write to the device in a variety of ways. For example, if you wish to interface to a standard bus such as serial peripheral interface (SPI), I2C, parallel, etc., the Quartus II software automates the interface through a GUI-based megafunction.

User Flash Memory Applications

The MAX® II CPLD family is a non-volatile, instant-on programmable logic family using an industry-first CPLD architecture that allows you to reduce system power, space, and cost.

  • MAX II CPLD Family (MAX II, MAX IIG, MAX IIZ)
  • Package and I/O Offering
  • Speed Grade Offering
  • Industrial Temperature Support
  • Features
  • Questions and Answers

The foundation of lower system cost and power savings is an architecture combining all of the advantages of Intel's MAX II CPLDs, while leveraging Intel's expertise in FPGA products and look-up table (LUT)-based architectures. The LUT-based architecture delivers the maximum logic capability in the smallest I/O pad-constrained space.

MAX II CPLDs are used for a wide variety of applications previously implemented in older generation FPGAs, ASSPs, and standard-logic devices.

Architectural and Board Management

MAX II CPLD Features at a Glance

Feature Description
Cost-Optimized Architecture Altera® MAX II CPLDs have a new CPLD architecture that breaks through traditional macrocell power, space, and cost limitations.
Low Power MAX II CPLDs offer the lowest dynamic power in the CPLD industry with one-tenth the power of previous MAX CPLDs.
Features Unique to MAX II CPLDs MAX II CPLDs offer 8 Kbits of user-accessible flash memory to implement on-chip serial or parallel non-volatile storage.
Real-Time In-System Programmability (ISP) MAX II CPLDs allow you to update the configuration flash memory while the CPLD is in operation.
I/O Capabilities MAX II CPLDs support a variety of single-ended I/O interface standards such as LVTTL, LVCMOS, and PCI.
Packages Available Thin quad flat pack (TQFP), 1.0-mm pitch FineLine BGA (FBGA), and 0.5-mm pitch Micro FineLine BGA (MBGA).
Parallel Flash Loader MAX II CPLDs feature a JTAG block that can configure external non-JTAG-compliant devices such as discrete flash memory devices using the Parallel Flash Loader megafunction.
Industrial Temperature Support MAX II CPLDs support the industrial temperature range, -40°C to +100°C (junction), required for various industrial and other temperature-sensitive applications.
Extended Temperature Support MAX II CPLDs are offered in the extended temperature range, -40°C to +125°C (junction), to support automotive and other temperature-sensitive applications.

Intel® Max® II CPLD Reference Links