The MAX® II CPLD family from Intel is based on a groundbreaking architecture that delivers low power and low cost. With the introduction of the MAX® IIZ CPLD, there are now three variants that all use the same innovative CPLD architecture.

Family Variants


Learn more about all device variations and how specifications compare.

View overview table


Learn more about all device variations and how specifications compare.

View overview table


Learn more about all device variations and how specifications compare.

View overview table

This instant-on, non-volatile CPLD family targets general-purpose, low-density logic and portable applications, such as cellular handset design. In addition to delivering the lowest cost for traditional CPLD designs, the MAX® II CPLD drives power and cost improvements to higher densities, enabling you to use a MAX® II CPLD in place of a higher power or higher cost ASSP or and standard-logic CPLD.


The low-cost MAX® II CPLDs offer architectural and board management features to optimize ease of use and system integration. The MAX® II CPLD enables a high level of functional integration to reduce system design costs.

Cost-Optimized Architecture

MAX® II CPLDs have a new CPLD architecture that breaks through traditional macrocell power, space, and cost limitations.

Low Power

MAX® II CPLDs offer the lowest dynamic power in the CPLD industry with one-tenth the power of previous MAX® CPLDs.

Real-Time In-System Programmability (ISP)

MAX® II CPLDs allow you to update the configuration flash memory while the CPLD is in operation.

I/O Capabilities

MAX® II CPLDs support a variety of single-ended I/O interface standards such as LVTTL, LVCMOS, and PCI.

Packages Available

TQFP, 1.0-mm pitch FBGA, and 0.5-mm pitch MBGA.

Parallel Flash Loader

MAX® II CPLDs feature a JTAG block that can configure external non-JTAG-compliant devices such as discrete flash memory devices using the Parallel Flash Loader megafunction.

Industrial Temperature Support

MAX® II CPLDs support the industrial temperature range, -40°C to +100°C (junction), required for various industrial and other temperature-sensitive applications.

Extended Temperature Support

MAX® II CPLDs are offered in the extended temperature range, -40°C to +125°C (junction), to support automotive and other temperature-sensitive applications.

Design Tools

Designing with MAX® II CPLDs is easy. The design resources listed in the table provide you with technical information to help you learn about, evaluate, and begin designing with MAX® II CPLDs.

Download Literature and Early Power Estimator

You can download the most commonly referenced MAX II literature or simply browse through all of the MAX® II CPLD-related documents.

FPGA Design Software and Development Tools

Intel® Quartus® development software, customer acclaimed as easy to learn and even easier to use, allows you to exceed your performance goals, complete your design faster, and meet power budgets for your next-generation system designs by taking full advantage of the benefits of MAX® II CPLDs.

Check out the What's New in Quartus Prime Software web page for the latest features and new devices supported in the Intel® Quartus® Prime Software II. For details on how Quartus Prime software supports MAX® II CPLDs in particular, see the Easiest-to-Use Design Software for CPLDs web page.

Design Examples and IP Cores

We and our partners provide IP cores and reference designs you can use to accelerate your MAX® II CPLD design. Commonly used with MAX® II CPLDs are the PCI 32-bit master/target or PCI 32-bit target only, and the I2C master/slave IP cores. With OpenCore and OpenCore Plus versions of the cores, you can evaluate the IP cores before you buy them.

Starting Your Design

Development Kits and Boards

Whether designing for communications, consumer, computing, or industrial applications, MAX® II CPLDs offer low power and low prices, making them the ideal solution for complex control applications.

Development Kit Name

Featured Device


Price Vendor
MAX II Development Kit EPM1270

Data Sheet (PDF)


Intel (Buy Now)

MAX II Micro Kit EPM2210

User Manual (PDF)

$69 Terasic (Buy Now)


Whether designing for communications, consumer, computing, or industrial applications, MAX® II CPLDs offer low power and low prices, making them the ideal solution for complex control applications.

MAX® II CPLD Applications

Common control path functions can be divided into four main categories: interface bridging, I/O expansion, system configuration, and power-up sequencing.

Application Description
Interface Bridging Translate bus protocols and voltages between incompatible devices at the lowest possible cost.
I/O Expansion Perform I/O decoding, increasing the available I/O on a ASSP or microcontroller easily and at a low cost.
System Configuration and Initialization Control the configuration or initialization of volatile devices.
Power-Up Sequencing Manage the correct power-up sequencing for other devices on the board.
General-Purpose Logic MAX II features that serve general-purpose logic needs.
Portable Applications MAX® IIZ CPLDs make portable applications possible in the most demanding environments.
Wide-Input Functions Implementing Wide-Input Functions in MAX® II CPLDs.


Altera’s MAX II family of low-cost CPLDs was the first architecture introduced that combines the best of traditional CPLD architectures with Altera's innovative FPGA look-up table (LUT) logic structure. There are three MAX II family variants, all using the same basic architecture:


These devices are optimized for the lowest cost-per-I/O pin and target general-purpose, low-density logic applications. Many customers use MAX® II CPLDs as replacements for low-density FPGAs, ASSPs, and standard-logic devices.

Altera’s MAX® II CPLDs are ideal for price-sensitive, general-purpose, low-density logic applications such as interface bridging, I/O expansion, device configuration, and power-up sequencing. More information on these applications is available on the MAX® II Applications page. MAX® II CPLDs are also ideal for portable applications because they offer 50 percent lower cost and power than competing CPLDs.

The MAX® II CPLD family includes four members, ranging in density from 240 to 2,210 logic elements (LEs), and up to 272 user I/O pins. Devices are available with vertical migration support in low-cost thin-quad flat pack (TQFP), FineLine BGA (FBGA), and Micro FineLine BGA (MBGA) packages.

The MAX II device ordering codes are based on the number of available LEs in the device. All MAX® II CPLD ordering codes begin with EPM. The digits that follow indicate the number of LEs in that device.

There is no standard conversion ratio between LEs and macrocells, but based on empirical data extracted from hundreds of customer designs, Altera determined the typical "equivalent macrocell" ratio to be approximately 1.3 LEs per macrocell.

The MAX II device family is based on a cost-optimized 1.8-V, 0.18-µm, six metal-layer flash process from Taiwan Semiconductor Manufacturing Company (TSMC).

All MAX® II CPLDs are available now.

Altera currently recommends two low-cost development kits:

  • MAX II Development Kit (EPM1270)
  • MAX II Micro Kit (EPM2210)

Contact your local Altera sales representative for updates on MAX® IIZ kits.

The main differences between the MAX II variants are the necessary supply voltages required to power the device as well as the power consumption specifications.

Both device families are non-volatile and instant-on. The MAX II families are half the cost, consume one-tenth the power, and deliver four times the density of the MAX device family. The MAX device family is built on a macrocell-based architecture, while the MAX II device family is built on a LUT-based architecture.

The MAX II and Cyclone® device families were built to address different applications. The largest MAX II device offers 2,210 LEs, and the smallest Cyclone® device offers 2,910 LEs. The MAX II family consists of non-volatile and instant-on devices, while Cyclone® devices use a separate device for configuration. Despite these differences, there is an overlap in the number of I/O pins available in the MAX II and Cyclone® devices. In addition, while the two device families are comparable in cost per LE, MAX® II CPLDs will always be lower in cost per I/O pin.

The MAX II family’s power consumption is approximately one-tenth that of the previous-generation MAX CPLDs.

The standby current specification assumes the input voltage is zero (GND), there is no load, and no inputs toggling.

A MAX II low-power CPLD can be completely powered-down because of its superior hot-socket, power-sequence flexibility, and single power supply simplicity. More information on the power-down capability is available on the MAX II Low-Power page.

The MAX II family’s performance is on average twice as fast as the previous-generation MAX CPLDs.

The speed grades describe the relative speed of each device. The -3 is the fastest, the -4 is the medium, and the -5 is the slowest speed grade. The "fastest tpd1" specification in the MAX II Device Handbook correlates to the fastest commercial speed grade, which is a corner-to-corner delay path through the device.

For both the MAX II and Stratix® II families, the -3 speed grade is the fastest, -4 is the medium, and -5 is the slowest. Even though the speed grade nomenclature is the same, the performance specifications are not.

No. MAX® II CPLDs are based on a completely new architecture and are, therefore, not pin-compatible with Altera’s MAX 7000 or MAX 3000 device families.

Each MAX® II CPLD family member is optimized for the highest possible number of I/O pins in the lowest density device for a given package. Because of higher LE counts, high-density members require a greater number of power and ground pins to operate correctly. For any given package, therefore, the number of available user I/O pins must be reduced when a denser device is used.

The smallest MAX II device (EPM240) powers-on in less than 200 microseconds, from the time the supply voltage meets the minimum VCC. The EPM570 and EPM2210 devices power-up in less than 300 microseconds. The largest MAX II device (EPM2210) powers-on in less than 450 microseconds, from the time the supply voltage meets the minimum VCC.

The user flash memory allows you to integrate discrete serial or parallel non-volatile storage onto MAX® II CPLDs. The configuration flash memory, which is not user accessible, is employed internally to store the programmed design information that is subsequently loaded into the programmable logic.

Yes. The MAX® II CPLDs support in-system programmability (ISP) through the JTAG ports using .pof, JamTM STAPL, .svf, or IEEE 1532 files.

No. There are no PLLs available in MAX® II CPLDs. The die size, power requirements, and clock pins required for PLLs would have increased device cost above desired levels.

MAX® II CPLDs support a variety of single-ended I/O standards, including LVTTL, LVCMOS, and PCI. MAX® II CPLDs also support a programmable slew rate and drive strength control for certain I/O standards.

Yes. The VCCIO and VCCINT power pins can be powered-up in any order. In addition, signals can be driven into the MAX II devices before and during power-up (and power-down) without damaging the device, because device I/O pins do not source or sink more than 300 µA of DC current during these operations.

The MAX® II CPLDs have up to four I/O banks that seamlessly interface to other devices at 3.3-, 2.5-, 1.8-, and 1.5-V logic levels.

The two larger MAX® II CPLDs are 5.0-V tolerant when used with an external series resistor and the on-chip PCI clamping diode. The two smaller devices are not 5.0-V tolerant.

The two largest MAX® II CPLDs support 66-MHz, 32-bit PCI.

All MAX® II CPLDs are supported by the Quartus II Web Edition software version 4.0 or higher, which you can download for free. The full version of the Intel® Quartus® Prime Software II version 4.0 or higher, available through Altera’s subscription program, also supports all MAX II devices. Programming file generation for the MAX® II CPLDs will also be supported in a subsequent software release.

No. MAX® II CPLDs are supported in the Intel® Quartus® Prime Software II, versions 4.0 or higher.

Synthesis and simulation tools from leading EDA vendors Mentor Graphics® (Precision 2003C) and Synplicity (Synplify 7.5.1) support the MAX® II CPLD family to ensure the highest quality design implementation.

Altera offers a PCI core for the MAX® II CPLDs. Support will also be provided for a select number of common interfacing cores, including I2 C, SPI, and UARTs.

Documentation and Support

Find technical documentation, videos, and training courses for your Intel® MAX® II CPLD designs.