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Technical Specifications

Essentials

Status
Launched
Power Supply Type
AC
# of Power Supply Included
1
Redundant Fans
Yes
Rack Rails Included
Yes
# of Ports External
24
Operating Temperature Range
5°C to 40°C

Supplemental Information

Description
1U 24 Port 100 Gbps Switch based on the Intel® Omni-Path Architecture

Networking Specifications

Data Rate Per Port
100Gbps

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Optimizations and Enhancements

While similar to existing technology, Intel® Omni-Path Architecture (Intel® OPA) has been enhanced to overcome the scaling challenges of large-sized clusters. These enhancements include:

Intel® Omni-Path Architecture is designed to support high message rate traffic from each node through the fabric. With ever-increasing processing power and core counts in Intel® Xeon® processors and Intel® Xeon Phi™ processors, that means the fabric has to support high bandwidth as well as high message rate throughput.

Intel® OPA switch 48-port design provides for improved fabric scalability, reduced latency, increased density, and reduced cost and power. In fact, the 48-port ASIC can enable 5 hop configurations of up to 27,648 nodes, or over 2.3x what’s possible with current InfiniBand* solutions. Depending on fabric size, this can reduce fabric infrastructure requirements in a typical fat tree configuration by over 50 percent, since fewer switches, cables, racks, and power are needed as compared to today’s 36-port switch ASICs.

Features in Intel® OPA help minimize the negative performance impacts of large Maximum Transfer Units (MTUs) on small messages and help maintain consistent latency for interprocess communication (IPC) messages, such as Message Passing Interface (MPI) messages, when large messages—typically storage—are being simultaneously transmitted in the fabric. This will allow Intel® OPA to bypass lower priority large packets to allow higher priority small packets, creating a low and more predictable latency through the fabric.

Intel® Omni-Path Architecture also delivers efficient detection and error correction, which is expected to be much more efficient than forward error correction (FEC) defined in the InfiniBand standard. Enhancements include zero load for detection, and if a correction is required, packets only need to be retransmitted from the last link—not all the way from the sending node—which enables near zero additional latency for a correction.

Benchmarks for Intel® Omni-Path Architecture


See complete speed, performance, and configuration specs.

Product and Performance Information

This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.