Frequently Asked Questions About the 13th Gen Intel Core Processors

Performance-cores (P-cores):

  • Are optimized to handle single and lightly threaded performance.
  • Enhance gaming and productivity workload.

Efficient-cores (E-cores):

  • Are optimized to handle scaling highly threaded workloads.
  • Minimize interruptions from background task management.

Intel® Thread Director sends the right workload to the right core at the right time. It helps prioritize and manage the distribution of workloads, sending tasks to the most optimized thread. This feature is on by default and works in tandem with the operating system for intelligent workload distribution. To get the full capabilities of Intel Thread Director, pair a select 13th Gen Intel® Core™ desktop processor with Windows 112.

Intel provides the best memory or motherboard overclocking experiences3 for everyone from - experts to beginners. With an unlocked Intel core processor anyone can overclock using Intel® Extreme Tuning Utility with Intel® Speed Optimizer. Intel® Speed Optimizer provides a one click overclocking (removed memory comment) which makes the overclocking process easy.

Learn more about overclocking

Product and Performance Information


Performance hybrid architecture combines two core microarchitectures, Performance-cores (P-cores) and Efficient-cores (E-cores), on a single processor die first introduced on 12th Gen Intel® Core™ processors. Select 13th Gen Intel® Core™ processors do not have performance hybrid architecture, only P-cores, and have same cache size as prior generation; see for SKU details.


Built into the hardware, Intel® Thread Director is provided only in performance hybrid architecture configurations of 12th Gen or newer Intel® Core™ processors; OS enablement is required. Available features and functionality vary by OS.


Based on enhanced overclocking ability enabled by Intel's comprehensive tools and unique architectural tuning capabilities. Your results may vary. Overclocking may void warranty or affect system health. For details see