Stratix® V E FPGA

Optimized for ASIC prototyping with 952K logic elements on the highest performance logic fabric.

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Stratix® V E FPGA

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<script>var isTargetEnabled =false;</script>

<script type="text/javascript">
    var cq_tms = {
        wa_emtcontenttype: "emtcontenttype:salesandmarketingmaterials/productcatalog",
        wa_upeproducts: "upeproducts",
        
        wa_industry_type: "",
        wa_partner_prog: "",
        wa_subject: "",
        wa_biz_size: "",
        wa_emt_org: "",
        wa_emt_intel: "",
        wa_partner_type: "",
        wa_programidentifier: "upe",
        wa_location: "us",
        wa_language: "en",
        wa_english_title: "Stratix® V E FPGA Overview",
        wa_content_type: "productcatalog",
        wa_intel_platform: "",
        wa_applications: "",
        wa_local: "en_US",
        wa_intel_technology: "",
        wa_system_type: "",
        wa_product_name: "",
        wa_audience: "",
        wa_life_cycle: "",
        wa_cq_url: "/content/www/us/en/products/details/fpga/stratix/v/e.html",
        wa_page_type_micro: "upeproductscatalog",
        wa_env: "prd",
        wa_cq_pub_env: "publish",
        wa_transl_status: "",
        wa_product_id: "",
        wa_software: "",
        wa_reference_design: "",
        wa_codename: "",
        wa_created_date: "1617218602410",
        wa_modified_date: "1659488363305",
        wa_off_time: "1751305140000",
        wa_ownedby: "emtorganizationalstructure:datacenterandai/psgprogrammablesolutionsgroup",
        wa_managedby: "",
        wa_idz_nid : "",
        wa_event_type: "",
        wa_idz_custom_tags: "",
        wa_programming_language: "",
        wa_skill_level: "",
        wa_solution: "",
        wa_product_formFactor: "",
        wa_operating_system: "",
        wa_marketing_products: "",
        wa_ssg_third_party_prod_sys_sol: "",
        wa_upeNamespace: "upeproducts:intelfpgas/intelstratixseries/stratixvfpgas/stratixvefpga",
        wa_doc_id:"",
        wa_doc_version:"",
        wa_doc_publishdate:"",
        wa_intel_prd_levels: '[{"level4":{"id":"141557","desc":"stratixvefpga"},"level1":{"id":"98836","desc":"intelfpgas"},"level3":{"id":"147210","desc":"stratixvfpgas"},"productCategory":"upeproducts","level2":{"id":"2000000106","desc":"intelstratixseries"}}]',
        
        wa_secondary_content_type: ""
        
        ,wa_upeProducts: "upeproducts:intelfpgas/intelstratixseries/stratixvfpgas/stratixvefpga"
        
        
        
    };

cq_tms.wa_tms_sync_load = "deferred";
    
    
</script>

<script type="text/javascript">
    var chatContextObj = {};
    chatContextObj["locale"] = 'en-US';
    chatContextObj["app"] = 'PSG';
    chatContextObj["supportProductMap"] = 'NA';
</script>
<script src="/etc.clientlibs/settings/wcm/designs/ver/220921/intel/clientlibs/detect-idsa.min.js" defer></script>

<script type="text/javascript" src="/content/dam/www/global/wap/tms.sync.js" async></script>

<link rel="stylesheet" href="/etc.clientlibs/settings/wcm/designs/ver/220921/intel/clientlibs/pages/commons-page.min.css" type="text/css"><script src="/etc.clientlibs/settings/wcm/designs/ver/220921/intel/clientlibs/pages/commons-page.min.js" defer></script>

<script>!function(){var e=setInterval(function(){"undefined"!=typeof $CQ&&($CQ(function(){CQ_Analytics.SegmentMgr.loadSegments("/etc/segmentation"),CQ_Analytics.ClientContextUtils.init("/etc/clientcontext/intel",window.location.pathname.substr(0,window.location.pathname.indexOf(".")))}),clearInterval(e))},100)}();</script>

<link rel="preload" as="style" href="/etc.clientlibs/settings/wcm/designs/intel/us/en/css/resources/css/intel.rwd.override.css"/>
<link rel="stylesheet" type="text/css" href="/etc.clientlibs/settings/wcm/designs/intel/us/en/css/resources/css/intel.rwd.override.css"/>