Stratix® V FPGAs

Attain Breakthrough Bandwidth with Power-Efficient Transceivers

• Integrated 28.05- and 14.1-Gbps transceivers, with up to 50 percent lower transceiver power compared to previous-generation devices.
• Up to 6 x72 DDR3 memory interfaces at 933 MHz.
• 2.5 TMACS of signal processing performance.
• PCI Express* Gen3, Gen2, and Gen1 hard intellectual property (IP) support.

Achieve Higher Integration on a Single Chip and Reduce Your Costs

• Double the density without a cost and power penalty, through Embedded HardCopy Blocks, which deliver up to 14.3M ASIC gates or up to 1.19M logic elements. The blocks harden standard or logic-intensive functions including interface protocols like PCI Express* Gen3, Gen2, and Gen1, and application-specific functions like 40G/100G/400G.
• Partial reconfiguration, which enables you to reduce the size of FPGAs, saving board space, cost, and power.
• Fractional phase-locked loops (fPLLs), which provide increased clocking flexibility and replace on-board voltage-controlled crystal oscillators (VCXOs).
• Integrated electronic dispersion compensation (EDC) capability in transceivers, which eliminates the need for external PHY to interface to optical modules.

Get Ultimate Flexibility for Your Designs

• User-friendly fine-grain partial reconfiguration, which allows you to change core functionality on the fly.
• Dynamically reconfigurable transceivers, which let you easily support multiple protocols, data rates, and physical media attachment (PMA) settings.
• Configuration via Protocol (CvP) using the existing PCI Express* link in your application, which allows for a less complex board design.

Lower Your System Power

• Programmable Power Technology that maximizes core performance while simultaneously reducing power.
• TSMC's 28-nm high-K metal gate high-performance process optimized for lower power.
• 0.85-V/0.9-V core voltage.
• Partial reconfiguration.
• Embedded HardCopy Blocks and integrated core and transceiver hard IP.

Transceivers

Intel® transceivers have a proven track record of meeting system bandwidth, power, and bit-error rate (BER) requirements. The technology leadership continues with the transceivers in our 28 nm Stratix® V FPGAs.

Partial & Dynamic Reconfiguration

With Stratix® V FPGAs, you can easily change the core and transceiver functionality on the fly while other portions of your design are still running.

System Integration

Because Stratix® V FPGAs enable high system integration, you get increased functionality in a smaller FPGA, lowering power and cost. Here, we'll discuss a number of Stratix® V innovations that make this level of integration possible.

Fractional PLLs

Fractional phase-locked loops (fPLLs) offer all the features available in previous-generation Altera® PLLs. You can find fractional PLLs in Altera's 28 nm devices, including Stratix® V, Arria® V, and Cyclone® V FPGAs.