Stratix® IV FPGA Design Tools

Design Utility Description
General Resources  
Device family overview Find the right Stratix® IV FPGA to meet your design requirements.
Stratix® IV FPGA applications Learn about the end markets and applications for which Stratix® IV FPGAs are optimized.
High-speed serial I/O solutions center Find everything needed for implementing high-speed serial interfaces with Stratix® IV GX FPGAs, including technical documentation, protocols and IP, signal integrity details, and simulation models.
Signal integrity center Access Stratix® IV GX FPGA signal integrity design resources to help you develop, lay out, and verify your high-speed design.
Literature center See all Stratix® IV FPGA-related documentation.
Software Resources  
Intel® Quartus® Prime Software Learn how the Intel® Quartus® Prime software supports designing with Stratix® IV FPGAs.
IP and reference designs Select off-the-shelf IP core functions from Intel and Intel's partners. IP cores are optimized for Intel devices, reducing design and test time, and can be evaluated in hardware and simulation prior to licensing.

General

Title Description
Leveraging the 40 nm process node to deliver the world's most advanced custom logic device (PDF) This paper discusses 40 nm process benefits over prior nodes, including the 65 nm node and the more recent 45 nm node.
Intel at 40 nm: jitter-, signal integrity-, power-, and process-optimized transceivers (PDF) Discusses how Intel's 40 nm transceiver innovations enable superior jitter, noise, signal integrity, and BER performance at the minimum power.
40 nm power management and advantages (PDF) Learn how 40 nm benefits and Intel's Programmable Power Technology enable the lowest power for high-end FPGAs.

Related

Title Description
Increasing productivity with Quartus II incremental compilation (PDF) This paper describes how an incremental compilation flow can improve your productivity when designing for high-density, high-performance FPGAs.
Guidance for accurately benchmarking FPGAs (PDF) This paper presents a rigorous methodology for accurately benchmarking the capabilities of an FPGA architecture.
Basic principles of signal integrity (PDF) Learn how to overcome signal integrity issues by following good design techniques and simple layout guidelines described in this document.
Performing equivalent timing analysis between TimeQuest and Xilinx* trace (PDF) This paper covers the differences in timing analysis between TimeQuest and Xilinx’s Trace, and explains how to configure the tools to provide equivalent performance comparison.

Stratix® IV FPGA Reference Links