FPGA IPU Platform F2000X-PL
High-performance Agilex™ FPGA-based Cloud and Enterprise Infrastructure acceleration platform with 2 x 100 GbE network interfaces and the capability to support Infrastructure workloads such as Open Virtual Switch (OVS), storage, microservices-based cloud applications, and more.
Overview
- Built with Agilex™ 7 FPGA F-Series and Intel® Xeon® D Processor
- 2 x 100G bandwidth with 200G crypto block
- PCIe 4.0 x 16 host interface
- PCIe 4.0 x 16 interface from FPGA to both host CPU and Xeon-D processor
- Full height, 3/4 length, single slot PCIe form factor
- Programmable through Infrastructure Programmer Development Kit (IPDK), Data Plane Development Kit (DPDK), and Storage Performance Development Kit (SPDK)
Get Started
Browse solutions, production-ready COTS boards, and development tools and infrastructure.
Workload designs for the IPU Platform F2000X-PL are available through Altera and industry leading partners.
Open Virtual Switch (OVS)
Full OVS offload and hardware accelerated fast path.
For more information and demo request, contact sales.
Storage
Offload and/or acceleration of key storage workloads including NVMe over Fabrics, RoCE RDMA, reliable transport, compression and cryptography, with SPDK support enabling disaggregated storage architectures.
Read the NVMeoF-TCP solution brief ›
For information and demo request, contact sales.
Microservices-Based Cloud Applications
Breakthrough latency and throughput plus significant data center CAPEX/OPEX savings for microservices-based cloud applications.
Read the MIT white paper on Microservice Benchmarking on IPUs running Napatech Software ›
For information and demo request, contact sales.
Partner Offerings
Discover Altera-based partner offerings for FPGA board solutions in the Intel Partner Showcase.
Napatech
Learn more about Napatech F2070X IPU adapter.
Comparison Table
| Features | IPU Platform F2000X-PL | Napatech* IPU F2070X |
|---|---|---|
| Platform Category | ||
| Target Market | Cloud and Enterprise Infrastructure workloads | |
| Type | IPU Platform | IPU Adapter |
| FPGA | ||
| FPGA Device | Agilex™ 7 F-Series AGFC023 | |
| Logic Elements | 2,308K | |
| On-Chip Memory | 246 Mb | |
| DSP Blocks | 1,640 | |
| FPGA Memory | 4x4 GB DDR4 (ECC, 40b, 2666MT) | |
| Processor | ||
| Type | Intel® Xeon® D-1736 Processor | |
| # of Cores | 8 | |
| Threads | 16 | |
| Processor Base Frequency | 2.3 GHz | |
| Max Turbo Frequency | 3.4 GHz | |
| Cache | 15 MB | |
| CPU Memory | 2x8 GB DDR4 (ECC, 72b, 2900MT) | |
| CPU Storage | 64 GB NVMe in M.2 slot for SoC Operating System | |
| Memory | ||
| Flash | 2 GB | |
| Interfaces and Modules | ||
| PCI Express* | 4.0 x16 to host CPU 4.0 x16 between FPGA and SoC |
|
| QSFP28/56 Interface | x2 | |
| Network Interface | 2 x100 Gbps | |
| Dedicated 1G Management port (RJ45) | N/A | 1 |
| Baseboard Management Controller (BMC) | Cyclone® 10 LP (10CL080YU484C8G) | MAX® 10 FPGA |
| FPGA Interface Manager | Yes | ASAF |
| Mechanical, Thermal, and Power | ||
| Form Factor | Full height, 3/4 length | Full height, half length |
| Width | Single slot | Dual slot |
| Maximum Power Consumption | 150W | |
| Tools Support | ||
| Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs | Yes | |
| Quartus® Prime Software | Yes | |
| Data Plane Development Kit (DPDK) | Yes | |
| Storage Performance Development Kit (SPDK) | Yes | |
| Infrastructure Programmer Development Kit (IPDK) | Yes | |
| P4 | Yes | |
| Contact | Altera | Napatech |
IPUs are programmable through multiple open developer frameworks, including Infrastructure Programmer Development Kit (IPDK), Data Plane Development Kit (DPDK), and Storage Performance Development Kit (SPDK).
Infrastructure Programmer Development Kit (IPDK) is an open source, community-driven, vendor agnostic framework of APIs and drivers for infrastructure offload and management that runs on a CPU, IPU, DPU, or switch.