The Nios II embedded processor family is Altera’s second-generation soft embedded processor solution. The Nios II processor cores are 32 bit RISC processors that share a common instruction set architecture and are optimized for use in all of Altera's mainstream FPGA families. Visit the Nios II processor page for details.

The Nios II processor is made available as three distinct cores to provide you with maximum design flexibility while balancing system performance needs and logic element (LE) usage. All three cores are included in the Nios II development kits and are supported by the SOPC Builder design tool.

The Nios II processor family is made up of these cores:

Nios II/f (fast)–Highest performance, moderate FPGA utilization

Nios II/s (standard)–High performance, low FPGA utilization

Nios II/e (economy)–Modest performance, lowest FPGA utilization

By implementing a processor as a hardware description language (HDL)-coded intellectual property (IP) core, you get an exact-fit solution because you can choose the peripheral, performance, and processor mix that best suits your system needs. Hard macro implementations are essentially ASICs and do not have the same flexibility; they take so long to deploy that you can't benefit from the latest process technology. Soft core processors, on the other hand, can migrate immediately to the latest FPGA technology such as the Stratix® or Cyclone FPGA series. Also, standard microprocessor-based solutions are subject to obsolescence issues, whereas Nios II-based solutions resist obsolescence because they are constructed from re-targetable HDL.

The Nios II processor has a 32 bit RISC instruction-set architecture, whereas the first-generation Nios processor has a 16 bit instruction-set architecture. The Nios II processor reaches new levels of efficiency and performance over the Nios processor core because it consumes much fewer FPGA resources yet quadruples computational performance. The Nios II processor also simplifies the processor selection process by providing a set of pre-optimized cores targeting specific price (logic usage) and performance constraints.

The Nios II processor family can be used in a wide range of applications that require a general-purpose, 32 bit embedded microprocessor.

The Nios II processors are fully supported by all Altera SoC, FPGAs, and HardCopy ASICs.

The Nios II processor IP license is royalty-free, and perpetual which means it allows user to use the Nios II processor IP core forever and has no limit on the number of Nios II processors that can be used in a given design or a project. The Nios II processor IP license entitled a user to one year worth of support from Altera mySupport and feature updates. For new features, and Altera mySupport assistance users must renew their Nios II prcoessor IP licenses if it is not current within two releases of the ACDS version.

No. Synopsys® provides the Nios II DesignWare IP core, an ASIC optimized version of the Nios II Processor that can be used for ASIC migration as part of their DesignWare IP Suite. Contact Synopsys directly for more details.

The Nios II Embedded Design Suite (EDS) represents complete development tool suite for both the creation of Nios II processor-based microcontrollers as well as the programming of the target Nios II processor systems.

Multi-processor systems are one of the main benefits of the Nios II embedded processors. The only limitation on the number of processor cores is the resource limitation of the FPGA fabric.

The Avalon® interface specification is used for master and slave components to communicate with each other. For low latency, point-to-point interface, Avalon specifies a simple Avalon Streaming interface (Avalon-ST). For an interface where a processor's master interfaces with a peripheral slave, Avalon specifies an Avalon Memory Mapped interface (Avalon-MM).

System interconnect is logic that is used to connect master and slave components. This logic might be a bridge, a multiplexor, an arbitration controller. Qsys automatically generates system interconnect logic and connects master and slave ports efficiently allowing multiple master ports to operate simultaneously, which dramatically boosts system performance.

The Avalon system interconnect is a custom-built interconnect that is automatically generated by Qsys.

The Nios II processor family provide the basic architectural elements found in most modern 32 bit processors, including:

32 bit instruction size

32 bit data and address paths

32 general-purpose registers

32 external interrupt sources

Configurable instruction cache

Configurable data cache

Common interface to up to 256 custom instructions

Common interface for the integration of custom peripherals

Custom instructions are user-added hardware blocks that augment the arithmetic logic unit (ALU) of a CPU. Nios II processors fully support the use of custom instructions, allowing you to fine-tune your system hardware to meet performance goals. You can create up to 256 custom instructions per Nios II processor core used in the system. Similar to native Nios II instructions, custom instruction logic can take values from up to two source registers and optionally write back a result to a destination register.

The Nios II prcoesspr software development tool automatically generates a customized C/C++ run-time environment tailored to the system hardware. The Nios II Embedded Design Suite also simplifies project setup by supplying several software templates which can be used as “starter” files in developing custom firmware solutions.

Altera provides a complete software debugging solution via the Nios II EDS that enables debug to occur via an instruction set simulator (ISS) or directly to system hardware. Direct debugging of a Nios II processor system in hardware is enabled through a hardware-assisted debug module. The debug module is rich in features and provides run control, memory examination and modification, hardware breakpoints, data triggers, and processor trace under IDE control.

Several top embedded software tools providers offer support for the Nios II family of processors, providing operating systems, middleware, software libraries, IDEs, debuggers, co-verification tools, and more. View the complete list of up-to-date embedded tools providers.