Nios® II Processors
Nios® II processor, the world's most versatile processor, according to Gartner Research, is the most widely used soft processor in the FPGA industry. The Nios® II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), and applications processing needs. The Nios® II processor supports all Intel® FPGA and SoC families.
Product Discontinuance Notice
Intel is discontinuing selected Nios® II IP ordering codes in March 2024 due to product transition to Nios® V. Refer to PDN 2312 for more information.
Nios® II/f
Fast
Intel specifically designed the Nios II/f “fast” processor for high performance.
Nios® II/e
Economy
Intel specifically designed the Nios II/e "economy" processor cores to use the fewest FPGA logic and memory resources.
What's New
See what's new with the Nios® II processor and Nios® II Embedded Design Suite (EDS).
Benefits
Nios® II embedded processors provide an ideal embedded solution.
Flexibility
With the perfect fit of CPUs, peripherals, memory interfaces, and custom hardware peripherals to meet the unique demands of every new design cycle, Nios® II processors offer you tremendous flexibility where you need it.
Long Life Cycle
Nios® II processors can help product developers to maximize their return on a product by providing life cycle benefits at every stage of a product's life.
Low Cost
Nios® II embedded processor provides phenomenal cost flexibility, allowing you to choose the exact set of processors, peripherals, memory, and interfaces that you need for your application, without paying for features that you don’t need.
High Performance
Nios® II processors give you the ultimate flexibility to achieve the exact performance required for your embedded design, without overpaying for high clock frequency, power-hungry off-the-shelf processors.
JTAG Debug Module
The Nios® II processor architecture supports a Joint Test Action Group (JTAG) debug module that provides on-chip emulation features to control the processor remotely from a host PC.
Hardware Acceleration
Similar to hardware accelerators, custom instructions allow Nios® II processor designers to increase system performance by offloading portions of the software code to hardware functions.
Nios® II Processor Cores
Used by more designers than any other soft processor in the world, Nios® II embedded processors remain the industry-standard processor for FPGA design.
Features
What makes the Nios® II processor the world's most versatile processor?
Single-Cycle Hardware
Multiply and barrel shifter.
Custom Instructions
Up to 256 custom instructions and unlimited hardware accelerators.
External Vector Interrupt Controller
Get up to 32 interrupts per controller.
Advanced Exception Support
Separate Instruction and Data Caches
Configurable from 512 bytes to 64 KB.
Access up to 4 GB of External Address Space
Optional Tightly-Coupled Memory for Instructions and Data
Achieve Maximum DMIPS
Up to six-stage pipeline to achieve maximum DMIPS (Dhrystone 2.1 benchmark) per MHz.
Processor Performance Benchmarks
DMIPS (Dhrystones 2.1 benchmark) at Fmax by Device
| Devices | Nios® II /e Economy |
Nios® II /f Fast |
|---|---|---|
| Cyclone® IV GX DMIPS at MHz (Dhrystones 2.1 benchmark) |
30 at |
190 at 165 MHz |
| Cyclone V GX DMIPS at MHz (Dhrystones 2.1 benchmark) |
33 at 220 MHz |
192 at 170 MHz |
| Arria® V GX DMIPS at MHz (Dhrystones 2.1 benchmark) |
37.5 at 250 MHz |
226 at 200 MHz |
| Intel Arria I0 GX DMIPS at MHz (Dhrystones 2.1 benchmark) |
52.5 at 350 MHz |
305 at 270 MHz |
| Stratix® V (DMIPS at MHz (Dhrystones 2.1 benchmark) |
54 at 420 MHz |
385 at 350 MHz |
Applications
Application |
Nios II Processor Core |
Vendor |
Description |
|---|---|---|---|
| Power and cost sensitive | Nios II economy core | Intel | With as low as 600 logic elements, the Nios II economy processor core is ideal for microcontroller applications. The Nios II economy processor core, software tools, and device drivers are offered free of charge. |
| Real time | Nios II fast core | Intel | Absolutely deterministic, jitter free real-time performance with unique hardware real-time feature options
|
| Applications processing | Nios II fast core | Intel | With a simple configuration option, the Nios II fast processor core can use a memory management unit (MMU) to run embedded Linux* operating system. Both open source and commercially supported versions of Linux for Nios II processors are available. |
Intel FPGA Embedded Alliance
| Application | Nios II Processor Core | Vendor | Description |
|---|---|---|---|
| Safety critical | Nios II SC core | HCell | Certify your design for DO-254 compliance by using the Nios II safety critical procesor core along with the DO-254 compliance design services offered by HCell. |
Lockstep Dual Core |
Lockstep Solution | Intel | Utilize the flexibility of the Nios II processor and Intel's lockstep technology to provide systems with high diagnostic coverage, self-checking and advanced diagnostic features in full compliance with functional safety standards IEC 61508 and ISO 26262. |
Ecosystem
Embedded IP Suite
Getting Started
Start your design today with the Nios® II processor by purchasing one of the many development kits available.
Intel® FPGA development kits:
- All new kits include pre-packaged Nios® II processor design examples entitled "Board Update Portal"
- Getting started design consist of processor, Ethernet media access control (MAC) with HTML web server application.
Nios® II processor Getting Started Resources (download a design example, read product documentation, or take an instructor-led training class to get started):
- Download Nios® II processor documentation
- Download the Nios® II EDS (now included with the free Intel® Quartus® Prime Lite Edition software)
- Purchase a Nios® II processor development kit
- Take a Nios® II processor training course
- Get started with a Nios® II processor design example
- Visit the Nios® II processor forum in and interact with other Nios® II processor designers
To ship designs featuring the Nios® II processor, you will need to purchase a license for the Nios® II processor.
Design Tools
The Nios® II Embedded Design Suite (EDS) is a comprehensive development package for Nios® II software design.
Documentation and Support
Find technical documentation, videos, and training courses for your Intel® Nios® II processor designs.
Frequently Asked Questions
The Nios II embedded processor family is Altera’s second-generation soft embedded processor solution. The Nios II processor cores are 32 bit RISC processors that share a common instruction set architecture and are optimized for use in all of Altera's mainstream FPGA families. Visit the Nios II processor page for details.
The Nios II processor is made available as three distinct cores to provide you with maximum design flexibility while balancing system performance needs and logic element (LE) usage. All three cores are included in the Nios II development kits and are supported by the SOPC Builder design tool.
The Nios II processor family is made up of these cores:
Nios II/f (fast)–Highest performance, moderate FPGA utilization
Nios II/s (standard)–High performance, low FPGA utilization
Nios II/e (economy)–Modest performance, lowest FPGA utilization
By implementing a processor as a hardware description language (HDL)-coded intellectual property (IP) core, you get an exact-fit solution because you can choose the peripheral, performance, and processor mix that best suits your system needs. Hard macro implementations are essentially ASICs and do not have the same flexibility; they take so long to deploy that you can't benefit from the latest process technology. Soft core processors, on the other hand, can migrate immediately to the latest FPGA technology such as the Stratix® or Cyclone FPGA series. Also, standard microprocessor-based solutions are subject to obsolescence issues, whereas Nios II-based solutions resist obsolescence because they are constructed from re-targetable HDL.
The Nios II processor has a 32 bit RISC instruction-set architecture, whereas the first-generation Nios processor has a 16 bit instruction-set architecture. The Nios II processor reaches new levels of efficiency and performance over the Nios processor core because it consumes much fewer FPGA resources yet quadruples computational performance. The Nios II processor also simplifies the processor selection process by providing a set of pre-optimized cores targeting specific price (logic usage) and performance constraints.
The Nios II processor family can be used in a wide range of applications that require a general-purpose, 32 bit embedded microprocessor.
The Nios II processors are fully supported by all Altera SoC, FPGAs, and HardCopy ASICs.
The Nios II processor IP license is royalty-free, and perpetual which means it allows user to use the Nios II processor IP core forever and has no limit on the number of Nios II processors that can be used in a given design or a project. The Nios II processor IP license entitled a user to one year worth of support from Altera mySupport and feature updates. For new features, and Altera mySupport assistance users must renew their Nios II prcoessor IP licenses if it is not current within two releases of the ACDS version.
No. Synopsys® provides the Nios II DesignWare IP core, an ASIC optimized version of the Nios II Processor that can be used for ASIC migration as part of their DesignWare IP Suite. Contact Synopsys directly for more details.
The Nios II Embedded Design Suite (EDS) represents complete development tool suite for both the creation of Nios II processor-based microcontrollers as well as the programming of the target Nios II processor systems.
Multi-processor systems are one of the main benefits of the Nios II embedded processors. The only limitation on the number of processor cores is the resource limitation of the FPGA fabric.
The Avalon® interface specification is used for master and slave components to communicate with each other. For low latency, point-to-point interface, Avalon specifies a simple Avalon Streaming interface (Avalon-ST). For an interface where a processor's master interfaces with a peripheral slave, Avalon specifies an Avalon Memory Mapped interface (Avalon-MM).
System interconnect is logic that is used to connect master and slave components. This logic might be a bridge, a multiplexor, an arbitration controller. Qsys automatically generates system interconnect logic and connects master and slave ports efficiently allowing multiple master ports to operate simultaneously, which dramatically boosts system performance.
The Avalon system interconnect is a custom-built interconnect that is automatically generated by Qsys.
The Nios II processor family provide the basic architectural elements found in most modern 32 bit processors, including:
32 bit instruction size
32 bit data and address paths
32 general-purpose registers
32 external interrupt sources
Configurable instruction cache
Configurable data cache
Common interface to up to 256 custom instructions
Common interface for the integration of custom peripherals
Custom instructions are user-added hardware blocks that augment the arithmetic logic unit (ALU) of a CPU. Nios II processors fully support the use of custom instructions, allowing you to fine-tune your system hardware to meet performance goals. You can create up to 256 custom instructions per Nios II processor core used in the system. Similar to native Nios II instructions, custom instruction logic can take values from up to two source registers and optionally write back a result to a destination register.
The Nios II prcoesspr software development tool automatically generates a customized C/C++ run-time environment tailored to the system hardware. The Nios II Embedded Design Suite also simplifies project setup by supplying several software templates which can be used as “starter” files in developing custom firmware solutions.
Altera provides a complete software debugging solution via the Nios II EDS that enables debug to occur via an instruction set simulator (ISS) or directly to system hardware. Direct debugging of a Nios II processor system in hardware is enabled through a hardware-assisted debug module. The debug module is rich in features and provides run control, memory examination and modification, hardware breakpoints, data triggers, and processor trace under IDE control.
Several top embedded software tools providers offer support for the Nios II family of processors, providing operating systems, middleware, software libraries, IDEs, debuggers, co-verification tools, and more. View the complete list of up-to-date embedded tools providers.
Additional Resources
Explore more content related to Intel® FPGA devices such as development boards, intellectual property, support and more.
Support Resources
Resource center for training, documentation, downloads, tools and support options.
Development Boards
Get started with our FPGA and accelerate your time-to-market with Intel-validated hardware and designs.
Intellectual Property
Shorten your design cycle with a broad portfolio of Intel-validated IP cores and reference designs.
FPGA Design Software
Explore Quartus Prime Software and our suite of productivity-enhancing tools to help you rapidly complete your hardware and software designs.
Contact Sales
Get in touch with sales for your Intel® FPGA product design and acceleration needs.
Where to Buy
Contact an Intel® Authorized Distributor today.