Leveraging the successful MAX® II architecture, MAX® V devices combine instant-on, non-volatile CPLD characteristics with advanced features typically found in FPGAs, on-chip memory, and internal oscillators.
Designed for Low Cost
MAX® V CPLDs are built using a low-cost fab process combined with a selection of popular, low-cost packages. A pad-limited, staggered I/O pad arrangement results in a small die size, as well as a low-cost-per-I/O pin.
Designed in Concert with Quartus Prime Software
To simplify the design optimization process, the MAX® V CPLD architecture and Quartus® Prime software fitting algorithms were refined in concert to optimize tPD, tCO, tSU, and fMAX performance with pins locked down. As design functionality changes, Quartus Prime software enhances the ability to meet or exceed performance requirements using locked pin assignments and a push-button compilation flow. All MAX® V CPLDs are supported by the free Quartus® Prime Lite Edition software.
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