JESD204C Intel® FPGA IP

The JESD204C Intel FPGA IP is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to FPGA devices.

Read the JESD204C Intel FPGA IP user guide ›

Read the JESD204C Intel® Agilex™ FPGA IP Design Example user guide ›

Read the JESD204C Intel® Stratix® 10 FPGA IP Design Example user guide ›

Read the JESD204B Intel FPGA IP user guide ›

JESD204C Intel® FPGA IP

The Intel FPGA IP incorporates:

  • Media access control (MAC)—data link layer (DLL) and transport layer (TL) blocks that control the link states.
  • Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.

Features

The JESD204C Intel FPGA IP core delivers the following key features:

  • Data rate of up to 28.9 Gbps for Intel Agilex and Intel Stratix 10 (E-tile) devices.
  • Single or multiple lanes (up to 16 lanes per link)
  • Local extended multiblock clock (LEMC) counter based on E=1 to 256
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multidevice synchronization
  • MAC and PHY partitioning
  • Deterministic latency support
  • 64/66 encoding
  • Scrambling/descrambling 
  • Avalon® streaming interface for transmit and receive datapaths
  • Avalon memory-mapped interface for control/status registers (CSR)
  • Dynamic generation of simulation test bench
  • Bonded and non-bonded TX PMA mode
  • Optional support for ECC M20K DCFIFO
  • Options for sync header configurations
  • CRC-12
  • Stand-alone command channels

IP Quality Metrics

Basics

Year IP was first released

2019

Latest version of Intel® Quartus® Prime Design Software supported

20.3

Status

Production

Deliverables

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Simulation model for ModelSim*- Intel FPGA Edition

    Timing and/or layout constraints

    Documentation with revision control

    Readme file

  • Y
  • Y
  • Y (included in user guide)
  • N

Any additional customer deliverables provided with IP

N/A

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode support

Y

Source language

Verilog and VHDL (at wrapper-level)

Testbench language

Verilog

Software drivers provided

N

Driver operating system (OS) support

N

Implementation

User interface

Avalon-ST (Datapath) and Avalon-MM (CSR)

IP-XACT metadata

N

Verification

Simulators supported

VCS, VCSMX, NCSIM, MODELSIM, XCELLIUM

Hardware validated

Y, on Intel FPGA Development Kits

Industry-standard compliance testing performed

Y

If Yes, which test(s)?

Electrical testing

If Yes, on which Intel FPGA device(s)?

Intel Stratix 10, Intel Agilex

If Yes, date performed

N/A

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Intel Stratix 10

Interoperability reports available

Y

Product and Performance Information

1

Retail prices reported as of 26 Jan 2022 19:05:10 GMT