JESD204C Intel® FPGA IP

IP Quality Metrics

Basics

Year IP was first released

2019

Latest version of Intel Quartus Prime Software supported

22.2

Status

Production

Deliverables

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Simulation model for ModelSim*-Intel FPGA Edition

    Timing and/or layout constraints

    Documentation with revision control

    Readme file

Y

Y

Y (included in user guide)

N

Any additional customer deliverables provided with IP

N/A

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode support

Y

Source language

Verilog and VHDL (at wrapper-level)

Testbench language

Verilog

Software drivers provided

N

Driver operating system (OS) support

N

Implementation

User interface

Avalon-ST (Datapath) and Avalon-MM (CSR)

IP-XACT metadata

N

Verification

Simulators supported

VCS, VCSMX, NCSIM, MODELSIM, XCELLIUM

Hardware validated

Y, on Intel FPGA Development Kits

Industry-standard compliance testing performed

Y

If Yes, which test(s)?

Electrical testing

If Yes, on which Intel FPGA device(s)?

Intel Stratix 10, Intel Agilex

If Yes, date performed

N/A

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Intel Stratix 10

Interoperability reports available

Y