Intel® Quartus® Prime Design Software
The intuitive high-performance design environment. From design entry and synthesis to optimization, verification, and simulation, Intel® Quartus® Prime Design Software unlocks increased capabilities on devices with multi-million logic elements, providing designers with the ideal platform to meet next-generation design opportunities.
Intel® Quartus® Prime Design Software
Platform Designer
Platform Designer is a system integration tool in the Intel® Quartus® Prime Software that automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems, saving significant time and effort in the FPGA design process.
Block-Based Design
Design, implement, and verify core or periphery blocks once, and then reuse those blocks multiple times across different projects that use the same device.
Partial Reconfiguration
Reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function.
Design Partition Planner
A design partition is a logical, named, hierarchical boundary that you can assign to an instance in your design. Defining a design partition allows you to optimize and lock down the compilation results for individual blocks.
Chip Planner
Chip Planner simplifies floorplanning by allowing you to view and constrain design logic within a visual display of the FPGA chip resources. You can use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter.
Interface Planner
The Interface Planner explores a device’s peripheral architecture and efficiently assigns interfaces. The Interface Planner prevents illegal pin assignments by performing fitter and legality checks in real-time.
Logic Lock Regions
A Logic Lock region is a powerful type of logic placement and routing constraint. You can define any arbitrary region of physical resources on the target device as a Logic Lock region, and then assign design nodes and other properties to the region.
Multiprocessor Support (Faster Compile Time)
Using multi-processors for compilation can result in faster compile times depending on the number of cores used.
IP Base Suite
Intel provides full production licenses for some of its popular intellectual property (IP) cores in the Intel® FPGA IP Base Suite, which is free with the Intel® Quartus® Prime Software and Intel Quartus Prime Pro Edition Software.
Fitter (Place and Route)
The Compiler's Fitter performs design placement and routing. During place and route, the Fitter determines the best placement and routing of logic in the target FPGA device.
Register Retiming
Register Retiming can balance register chains by retiming (moving) ALM registers into Hyper-Registers in the routing fabric.
Timing Analyzer
The Timing Analyzer is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry-standard constraint, analysis, and reporting methodology.
Design Space Explorer II
The Design Space Explorer II tool allows you to find optimal project settings for resource, performance, or power optimization goals.
Power Analysis
Power analysis features include Early Power Estimators, Intel® FPGA Power and Thermal Calculator, and the Power Analyzer that give you the ability to estimate power consumption.
Signal Tap Logic Analyzer
The Signal Tap logic analyzer captures and displays the real-time signal behavior in an Intel FPGA design allowing you to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment.
Transceiver Toolkit
Transceiver Toolkit uses System Console technology to help FPGA and board designers validate transceiver link signal integrity in real-time in a system and improve board bring-up time.
Questa*-Intel® FPGA Edition Software
Questa*-Intel® FPGA and Questa*-Intel® FPGA Starter software editions are a version of the Siemens EDA Questa* Core software targeted for Intel® FPGAs devices.
Intel® Advanced Link Analyzer Tool
The Intel® Advanced Link Analyzer is a state-of-the-art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance.
Intel® HLS Compiler
The Intel® HLS Compiler is a high-level synthesis (HLS) tool that takes in untimed C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel® FPGAs.
DSP Builder for Intel® FPGAs
DSP Builder is a digital signal processing design tool that enables Hardware Description Language generation of DSP algorithms directly from the MathWorks Simulink environment onto Intel® FPGAs.
Nios® Soft Processors for Intel® FPGAs
The Nios® soft processors are designed specifically for Intel® FPGAs. The soft processor series is suitable for a wide range of embedded computing applications, from digital signal processing to system control.
The Intel® SoC FPGA Embedded Development Suite (EDS)
The Intel® SoC FPGA EDS is a comprehensive tool suite for embedded software development on Intel® SoC FPGAs. It comprises of development tools, utility programs, run-time software, and application examples.