Cyclone® V FPGA and SoC FPGA

The multiport memory controller IP supports the following features:

• User configurable timing parameters set during compilation or during FPGA operation.
• Support for up to 4 Gb memory device per chip select.
• Two chip selects.
• Configurable memory width of 8, 16, 24, 32, and 40 bits.
• Hard error correction code (ECC) support for 16-bit and 32 bit data widths.
• Flexible fabric interface port configuration with up to six command ports and up to 256 bits of data.
• Bonding of two controllers to service higher bandwidth applications by creating a virtual x64 memory.
• DRAM power savings, including auto-refresh and deep power down.

The multiport memory controller consists of two major blocks as shown in Multiport Memory Controller Architecture diagram:

• Multiport front end—handles the arbitration of memory reads and writes between up to six masters.
• PHY—interfaces between the memory controller and the memory devices. Performs the actual read and write operations to and from the external memory.

The multiport front end provides the following arbitration and reordering features:

• Command and data reordering to boost bus efficiency.
  
• Out-of-order execution of DRAM commands.
• Collision detection and in-order return of results.
• Dynamically configurable priority support with both absolute and relative priority scheduling.

The PHY interface on the multiport memory controller offers the following calibration features for data sequencing and timing control:

• Hardened read FIFO buffer in input register path.
• Dedicated DDR registers in the I/O elements.
• Dynamic deskew delays with 25 ps resolution to optimize the sampling window.
• Skew adjustment circuitry to allow full path calibration from FPGA logic to the memory device on both read and write paths.
• On-chip termination calibration to limit termination impedance variation.
• On-chip dynamic termination to swap between serial and parallel termination for optimal signal integrity.
• DLL delay chain for temperature-compensated DQS phase shifts.

The multiport memory controller hard IP in the Cyclone® V FPGA supports DDR3 SDRAM, DDR2 SDRAM, and LPDDR2 (single-rank support only). The Cyclone® V FPGA also supports the soft memory controllers for the memory interfaces mentioned.

Accurate Power Estimation and Analysis

Intel makes power estimation and analysis from design concept through implementation easy, with the most accurate and complete power management design tools in the industry. Intel offers the following power estimation and analysis resources:

• Early power estimators.
• Intel® Quartus® Prime Software power analysis and optimization technology.
• Power Management Resource Center.

When designing, you can use the early power estimator (EPE) during the design concept phase and the power analyzer during the design implementation phase. The EPE is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization. The power models in the EPE are correlated to silicon, ensuring an accurate estimation of your design's power consumption.

The power analyzer is a far more detailed power analysis tool that uses actual design placement and routing, logic configuration, and simulated waveforms to estimate dynamic power very accurately. The power analyzer, in aggregate, provides approximately 10-percent accuracy when used with accurate design information. Intel® Quartus® Prime Software power models are correlated to silicon measurements based on over 5,000 test configurations per circuit.

Throughout the design process the Power Management Resource Center provides useful information regarding power, thermal management, and power supply management.

Intel® Quartus® Prime Software Optimization

Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area tradeoffs have been automated within the register transfer level (RTL) through the place-and-route design flow. Intel has taken a leadership position in bringing power optimization into the design flow. Intel® Quartus® Prime Software optimization tools automatically use the Cyclone® V architecture capabilities to reduce power further, resulting in up to 10 percent lower total power consumption when enabled.

The Intel® Quartus® Prime Software optimization has many automatic power optimizations that are transparent to you but provide optimal utilization of FPGA architecture details to minimize power, including:

• Transforming major functional blocks
  
• Mapping user RAM so they use less power
• Restructuring logic to reduce dynamic power
• Correctly selecting logic inputs to minimize capacitance on high-toggling nets
• Reducing area and wiring demand for core logic to minimize dynamic power in routing
• Modifying placement to reduce clocking power