Intel® Cyclone® 10 LP FPGA
Intel's Cyclone® 10 LP FPGA family extends the Intel Cyclone FPGA series leadership in low-cost and low-power devices. Ideal for high-volume, cost-sensitive functions, Intel Cyclone 10 LP FPGAs are designed for a broad spectrum of general logic applications.
See also: Intel® Cyclone® 10 LP FPGA Design Software, Design Store, Downloads, Community, and Support
Intel® Cyclone® 10 LP FPGA
Architecture
The logic and routing core fabric sea of gates is surrounded on each side by I/O elements, with a phase-locked loop (PLLs) in each corner. Embedded memory blocks (M9K) and 18 x 18 bit multipliers blocks are arranged in vertical columns.
The architecture also includes highly efficient interconnect and low-skew clock networks, providing connectivity between logic structures for clock and data signal.
Single Event Upset (SEU)
Configuration error detection is supported in all Intel® Cyclone® 10 LP devices. User mode error detection is only supported in devices with 1.2-V core voltage. Dedicated circuitry built into Intel® Cyclone® 10 LP devices consists of a CRC error detection feature that can optionally check for a single-event upset (SEU) continuously and automatically.
In critical applications used in the fields of avionics, telecommunications, system control, medical, and military applications, it is important to be able to:
- Confirm the accuracy of the configuration data stored in an FPGA device.
- Alert the system to an occurrence of a configuration error.
Nios® II Processor
Nios® II processor, the world's most versatile, royalty-free processor according to Gartner Research is the most widely used soft processor in the FPGA industry. The Nios II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), and ASIC-optimized applications processing needs.
The Nios II processor family consists of two configurable 32 bit Harvard architecture cores:
- Fast (/f core): Six-stage pipeline optimized for highest performance, optional memory management unit (MMU), or memory protection unit (MPU).
- Economy (/e core): Optimized for smallest size, and available at no cost (no license required).
Need to boost performance? No problem. Hardware acceleration is as easy as using an FPGA's programmable logic to offload and accelerate tasks that are typically implemented in an application software. Find out more on the Nios® II Processor web page.
For more information on free software development tools, visit the Nios® II Processor Design Tools web page.
For Nios II processor training, visit the Intel® FPGA Technical Training web page.
Nios® II Processor Applications
Application |
Nios® II Processor Core |
Vendor |
Description |
|---|---|---|---|
Power and cost sensitive |
Nios® II economy core |
Intel® |
With as low as 600 logic elements, the Nios II economy processor core is ideal for microcontroller applications. The Nios II economy processor core, software tools, and device drivers are offered free of charge. |
Real Time |
Nios® II fast Core |
Intel® |
Absolutely deterministic, jitter-free real-time performance with the following unique hardware real-time feature options:
|
Applications processing |
Nios® II fast core |
Intel® |
With a simple configuration option, the Nios® II fast processor core can use a memory management unit (MMU) to run embedded Linux*. Both open source and commercially supported versions of Linux for Nios II processors are available. |
Safety Critical |
Nios® II SC core |
HCELL |
Certify your design for DO-254 compliance by using the Nios® II Safety Critical processor core along with the DO-254 compliance design services offered by HCELL. |
Lockstep Dual Core |
fRSmartComp IP |
Yogitech |
The lockstep solution provides high diagnostic coverage, self-checking, and advanced diagnostic features in full compliance with functional safety standards IEC 61508 and ISO 26262 while reducing the need for difficult-to-develop and performance-sapping diagnostic software test libraries. |
Configuration error detection is supported in all Intel® Cyclone® 10 LP devices. User mode error detection is only supported in devices with 1.2-V core voltage. Dedicated circuitry built into Cyclone 10 LP devices consists of a CRC error detection feature that can optionally check for a single-event upset (SEU) continuously and automatically.
In critical applications used in the fields of avionics, telecommunications, system control, medical, and military applications, it is important to be able to:
- Confirm the accuracy of the configuration data stored in an FPGA device.
- Alert the system to an occurrence of a configuration error.
Qualification and Certification
Intel® Cyclone® 10 LP FPGAs are offered in commercial, industrial, and automotive (AEC-Q100) temperature grades.
In addition, they will be supported in a future release of the functional safety pack, TUV certified to IEC 61508, reducing development time and time to market.
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