The packaging technologies used to manufacture or assemble three basic types of component packages are summarized in this chapter. The package families, described in Chapter 1, provide the functional specialization and diversity required by device and product applications. Material and construction ...attributes of individual family members are provided by the following package technologies: (1) fired ceramic, (2) pressed ceramic, and (3) molded plastic. Intel’s packaging technology using organic substrates will be discussed in chapters 13, 14, and 15. Cartridge packaging assembly will be discussed in Chapter 16. Each of the three package families described in this chapter have some similar process steps but, the packaging materials and the form factors are uniquely different. The assembly core technology process steps (die attach, wire bond, lid seal, finish) are most commonly used in the industry today. However, several form factor modifications, driven on one hand by the advent of “Surface Mount Technology” (Quad Flat Pack packages and Ball Grid Array) and on the other hand by area array package socketing requirements (Pin Grid Array) are now the more commonly used form factors for microprocessors. This chapter will review in detail those core packaging technologies that are common to most of the standard IC package family types, i.e. DIPs, QFPs & Ceramic PGAs.
Die Preparation: Intel's die preparation consists of wafer mount and wafer saw process. Intel protects the active surface of wafers from handling-induced defects by using a contactless wafer mounting process. The wafer is mounted to a mylar tape to ensure the die is in place during and after sawing process. The mounted wafer is sawn into singulated die followed by high pressure deionized (DI) water wash. The wafer wash process is properly characterized to ensure no silicon dust and static charge build-up which will induce passivation damage. Intel uses 100% wafer saw through process to prevent die chipping.