This Intel® Itanium® Processor Family Error Handling Guide describes error handling on Itanium®-based systems. It provides guidelines for firmware and operating systems to take advantage of the Itanium Advanced Machine Check Architecture. This document references the Processor Abstraction Layer (PAL) and System Abstraction Layer (SAL) specifications and shows how firmware, platform desi...gn, and the operating system cooperate to address corrected errors and machine check aborts.
This document is intended for Itanium architecture SAL developers, platform designers, and OS developers. Implementation-specific details of processors are not discussed in this document. The target audience is expected to be familiar with the PAL and SAL specifications.