This document is an update to the specifications contained in the Affected Documents table. This document is a compilation of device and documentation errata, specification clarifications, and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.
Information types defined in the Nomenclature section are consolidated i...nto the specification update and are no longer published in other documents.
This document may also contain information that was not previously published.
The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® Core™ i7 processor extreme edition and Intel® Core™ i7 desktop processor product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
AAJ1. MCi_Status Overflow bit may be incorrectly set on a single instance of a DTLB error
Problem: A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the Overflow (bit ) in the MCi_Status register. A DTLB error is indicated by MCA error code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status register.
Implication: Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate indication of multiple occurrences of DTLB errors. There is no other impact to normal processor functionality.
Workaround: None identified.
Read the full Intel® Core™ i7 Processor Specification Update.