Key Features: VESA® Display Stream Compression (DSC) 1.2b compliant, supports all DSC 1.2b mandatory and optional encoding mechanisms, backward compatible to DSC v1.1. Configurable maximum display resolution up to 8K (FUHD). 8, 10, 12 bits per video component YCbCr and RGB video output format 4:4:4, 4:2:2, and 4:2:0 native coding, 1 pixel / clock internal processing architecture in 4:4:4, 2 pixels / clock internal processing architecture in 4:2:2 and 4:2:0 .Parameterizable number of parallel slice encoder instances (1, 2, 4, 8) to adapt to the capability of the technology and target display resolutions used, support for Intel® Arria®, Stratix®, and Agilex™ FPGAs • AXI-S (VPP-Lite) streaming interfaces for easy integration in the Intel® plaform designer tool. Avalon memory-mapped interface for register access. Compliant solution for DisplayPort 1.4™ or HDMI® 2.1o Compatibility for slices per line requirements when using a frame buffer ,supports flexible usage models and design architecture.