I3C-S: MIPI I3C Basic Slave Controller
About this offer
The I3C-S core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Slave controller core suitable for any I3C bus topology & compliant with the latest MIPI I3C-BasicSM specification. The highly featured slave-only core communicates in Single Data Rate (SDR) mode, but can tolerate High Data Rate (HDR) traffic. It can coexist and communicate with legacy I2C devices, and it can optionally be configured to operate as such in an I3C or I2C bus. The I3C-S needs no firmware support to parse and execute the broadcast or direct Common Command Codes (CCCs) relevant to I3C Basic Slaves. It can be assigned a Dynamic Address by the bus master, or use its legacy I2C static address, it supports Hot Join and is capable of generating In-Band Interrupts when directed by the host to do so. Designed for easy integration, the I3C-S can operate in two different modes. Under normal mode, data from private I3C or legacy I2C write transfers are stored to a FIFO, and made available to the host via an APB Slave interface. In a similar way, the host provides data to be used for private I3C or legacy I2C read transfers via the core’s APB slave interface. Alternatively, the core can operate in I3C-to-AHB bridging mode, where it autonomously converts private I3C or legacy I2C transfers to accesses on its AHB master port using a simple yet configurable over-I3C protocol. Under the I3C-to-AHB bridging mode, the core needs no software assistance and provides the I3C-master access to the local AHB bus, enabling remote monitoring, configuration, debug, or data exchange. The selection between normal and bridging operation modes is under software control via the core’s control register. The highly flexible core offers synthesis-time and run-time configuration options, which allow adapting its size and behavior to the application requirements. For example, the AHB-master interface and the clock domains synchronizers can be removed at synthesis time to reduce the core’s silicon footprint. During run-time, the I3C private data and I2C traffic can be bridged to the core's AHB master interface or transferred to and from the host via the core's APB slave interface. Also, parameters defining the CCCs processing (e.g. own-address, provisional ID, acknowledge for different type CCCs), the over-I3C protocol (i.e. number address bytes, max number of data bytes), and the AHB-master port behavior (e.g AHB burst type & address wrapping) are all run-time configurable via the core’s registers. The core is available in synthesizable Verilog format or as a targeted FPGA netlist, and its deliverables include everything required for successful implementation, including a system-Verilog test-bench, synthesis, and simulation scripts, and comprehensive documentation.
Details
Regional Coverage
Americas:
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Asia, Pacific, and Japan:
Southeast Asia
Australia and New Zealand
Japan
Taiwan
Rest of Asia
Korea
South Asia
Europe, Middle East, and Africa:
Middle East, Turkey, and Africa
Central Eastern Europe
Western European Union Region
Northern European Union Region
Southern European Union Region
Central European Region
People's Republic of China:
People's Republic of China
Use Case
Cloud Computing
Telematics
Environmental Monitoring
Industry
Manufacturing
Automotive
Defense and Space
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: Interface Protocols: Serial
- End Customer Type:
-
Small and Medium sized Business
Enterprise
Other
Included Intel Technology
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Cyclone® V FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs
Stratix® IV FPGAs
Intel® Cyclone® 10 FPGAs
Stratix® V FPGAs
Intel Agilex® 7 FPGAs and SoC FPGAs
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I3c-s: Mipi I3c Basic Slave Controller
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