Executive Summary High-Performance computing starts with the “Scale-Up” paradigm to get the most power into a single node. Over time we have seen the gigahertz race (Clock speed), a new more efficient internal bus architecture (PCIe), faster and faster memory, the addition of processor sockets and additional processing cores to each processor and the proliferation of 64-bit applications. While improvements will continue in these areas, it is the advent of the coprocessor first brings the ability to have a terraFLOP of processing power in a single server utilizing Intel® Xeon® processors.

Executive Summary 
High-Performance computing starts with the “Scale-Up” paradigm to get the most power into a single 
node. Over time we have seen the gigahertz race (Clock speed), a new more efficient internal bus 
architecture (PCIe), faster and faster memory, the addition of processor sockets and additional 
processing cores to each processor and the proliferation of 64-bit applications. While improvements will 
continue in these areas, it is the advent of the coprocessor first brings the ability to have a terraFLOP of 
processing power in a single server utilizing Intel® Xeon® processors.

Executive Summary High-Performance computing starts with the “Scale-Up” paradigm to get the most power into a single node. Over time we have seen the gigahertz race (Clock speed), a new more efficient internal bus architecture (PCIe), faster and faster memory, the addition of processor sockets and additional processing cores to each processor and the proliferation of 64-bit applications. While improvements will continue in these areas, it is the advent of the coprocessor first brings the ability to have a terraFLOP of processing power in a single server utilizing Intel® Xeon® processors.

Intel® Xeon Phi™ Coprocessor and Intel® True Scale Fabric

While the overall compute power in a single node is important, to further scale performance these nodes must be interconnected by a highly efficient network infrastructure. This paper will lay out the Intel® Xeon Phi™ coprocessor HW and SW environment and compare performance data on the Verbs and Offload InfiniBand* architecture to ...the Intel® True Scale Fabric with using the PSM/on-load architecture. To obtain best utilization from the a server utilizing the Intel® Xeon® processor and the Intel® Xeon Phi™ coprocessor, the Intel® coprocessor communications link (CCL) SW technology is required. There are two versions; an early version was released that supports the verbs/offload architecture. A succeeding release has been optimized for the Intel® True Scale Architecture PSM/on-load-based HCA. This Intel True Scale Architecture HPC networking infrastructure enables a clustered application to approach its maximum possible efficiency.

Read the full Intel® Xeon Phi™ Coprocessor and Intel® True Scale Fabric Overview.

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