IP Offerings

Two generations of experience building with Tri-Gate (FinFET) transistors and advanced double patterning techniques

We have two generations of experience building with Tri-Gate (FinFET) transistors and advanced double patterning techniques. The experience extends well beyond technology to include key fully co-optimized and silicon proven IP.

We offer a broad range of internally-developed IP that includes a library of Standard Cells, a full array of Memory Compilers, feature-rich Analog Cells and the world’s leading serializer/deserializer (SerDes). They have been optimized for power, performance, and area through numerous generations of refinement and production hardened in volume manufacture by our own products. Standard cell libraries come in a variety of track heights with extensive channel length, Vt and Vdd options. Memory SRAMs, ROMs, TCAMs and register files include a number of PORT configurations and power and area options.

"We evaluated many SerDes suppliers for our high performance Achronix* FPGAs. Both the 12.75G SerDes using Intel’s 22nm technology and the 32G SerDes using Intel's 14nm technology met our stringent power/performance requirements and the broad range of features that we needed,” said Robert Blake, CEO of Achronix. “The SerDes from Intel Custom Foundry is a key differentiating technology for the growing range of high-speed interfaces that our FPGAs require." 

Our analog IP offerings include an impressive array of SerDes interfaces that covers the full range of industry standards. They provide a high level of programmability and are fully optimized for industry-leading power, area and performance. Additional interface IPs are also available for memory, display, mobile and storage applications.

56G SerDes

The latest in interconnect technology, 56G PAM4 SerDes transfers data faster, meeting the bandwidth needs of modern high-performance ASICs.

Learn more about 56G SerDes

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