High Density Modular Test

Built for throughput, accuracy, and cost-effectiveness. Only available at Intel.

For Final Test, the Best Answer is H, D, M, and T

High Density Modular Test (HDMT) is the keystone of Intel’s internal test structure, purpose-built to address the challenges of modern final test. Beyond product quality, most test decisions are driven by the impact to unit cost and thus profitability. As its name implies, cost savings are derived by combining industry leading Automated Test Environment (ATE) capability and performance into a very small, modular package that can enable high throughput with low overhead.

Mobile Economics Put a Focus on Final Test

Modern flip chip system-on-chip (SoC) packages pose interesting economic challenges for test technology. Building a profitable business around high complexity, small die sold into increasingly competitive markets requires a low cost of goods sold. Final test technology must therefore meet a high bar: maintain low cost via high volume and low cycle times without sacrificing accuracy and thorough testing.

Enter HDMT

HDMT is our answer to those challenges. It is a singular test framework that represents a combination of hardware and software modules that can be configured to the device under test. The goal of its design was simply to break through the scalability limitations of traditional test equipment. By enabling flexibility in configuration and parallelism, capability and capacity can be optimized to the need of each individual product to achieve the lowest possible cost of test. Redundant engineering effort is eliminated with a singular test, thermal, and tooling environment. Lastly, the machine is fully integrated with our data feed forward network, representing a foundational link in our ability to provide unit-level process control and traceability in debug.

Powering Industry Leading Test Costs per Unit

Test cost per unit is a function of throughput, which itself is derived by units tested (cycle time) and overall setup time. HDMT is focused on the idea of maximizing the time spent testing, minimizing overhead and serialization through an asynchronous massively parallel handling architecture. This is all accomplished without regard to the complexity of the device test requirement – inclusive of adaptive test flows and complex in-situ decision making.

Converged Testing Environment Without Limiting Flexibility

When we set out to redefine final test, we recognized the obvious time-to-market savings of only building test tooling once as well as synchronizing the environments between prototyping and production. Our engineering and production environments are identical in every way, requiring zero correlation effort from single device under test to massive parallelism on complex devices.

Integrated Manufacturing Data

By integrating with our data feed forward network, each unit tested in the HDMT can be identified and traced from fabrication to shipping, which customers can review via the Intel Custom Foundry Services online portal. This streamlines debug at Final Test as all information about that unit is available for analysis, reducing the time to debug. Integrating all this information and placing responsibility with one manufacturer keeps projects on time and support costs low.

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