Presenters

Meet the keynote, panel, and plenary speakers.

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Joe Curley (Emcee)

Senior Director of Code Modernization Organization, Intel’s Data Center Group

Joe Curley serves Intel Corporation as Senior Director of Code Modernization Organization in Intel’s Enterprise and Government Group. His work focuses on programs designed to help ecosystem partners get the maximum benefit now and in the future from modern microprocessors and compute infrastructure. Joe joined Intel in 2007 to manage planning activities that lead up to the announcement of the Intel MIC Architecture in May of 2010. Prior to joining Intel, Joe worked at Dell Inc leading the Dell Precision Workstation and consumer/small business desktop products, as well as a series of engineering roles. He began his career at graphics pioneer Tseng Labs.

Welcome and Opening Keynote (Saturday, November 11, 2017 9:00-10:00 a.m.)

Gadi Singer

Vice President, Architecture General Manager, Artificial Intelligence Products Group at Intel Corporation 

Gadi Singer is Vice President at the Artificial Intelligence Products Group (AIPG) and General Manager of AIPG Architecture at Intel Corporation. Gadi has been driving Cognitive Computing programs across Intel groups and is responsible for developing multiple advanced compute engines. Gadi is currently overseeing the Intel® Nervana™ Neural Network Processor (NNP) architecture. Singer joined Intel in 1983, and has held a variety of senior technical and management positions in chip design, software engineering and CAD development. He was appointed vice president in 1999 and chief technical officer of Intel Communications Group in 2004. Before his current role at AIPG, he was vice president of the Platform Engineering Group and general manager of the integrated IP and technologies group architecture, responsible for the architecture of future IPs and leadership technologies for integration in Intel products and foundry including key subsystems such as CPU cores, graphics, imaging, security and audio, among others. Gadi also served as the general manager of the Intel Development Group z (IDGz) Architecture team. The IDGz Architecture Group was responsible for driving leading architecture (hardware and software), and capabilities across Intel’s Big Core products and SOCs. Prior to that Gadi served as general manager of the Software Enabling Group, responsible for driving leading architecture, practices, and capabilities across all IAG software development. Between 2011 and 2015, he held the position of general manager of Intel Israel Development Centers (IDC) and oversaw substantial growth in their scope and breadth. Among Singer's prior roles, he was general manager of the Ultra Mobility Group, general manager of the Microprocessor Products Group’s Design Technology Division, co-general manager of the IA-64 Processor Division and general manager of Enterprise Processors Division. His technological contributions include the invention of the Schematics Formal Verification (SFV) method at Intel, which establishes mathematical equivalence between design logic schematics to substantially reduce schematics functional bugs. He was also co-inventor of Intel’s Hardware Description Language (iHDL). Before joining Intel, Singer was a software engineer at Elbit Electronics in Israel from 1981 to 1983. He received his bachelor’s degree in electrical engineering from the Technion University, Israel, in 1983, and pursued graduate studies at Technion University from 1986 to 1988.

Al Gara

Intel Fellow and Chief Architect, Data Center Group, Intel Corporation

Dr. Al Gara is an Intel Fellow and Chief Architect of E&G Advanced Development, a part of Data Center Group at Intel Corporation. In this capacity he is leading a team of Intel architects in system pathfinding the future for Xeon-Phi compute directions. Additionally he is leading the Intel team responsible for delivering the Exascale system.

Prior to joining Intel in 2011, Dr. Gara was an IBM fellow and chief architect for three generations of the Blue Gene platforms which was awarded the National Medal of Technology and Innovation in 2008. Al has been the chief architect on more than 1/3 of the top10 systems over the last ten years as measured by the Top500.   Al has received two Gordon Bell prizes (1998 and 2006) and the Seymour Cray award in 2010. He has over 70 publications in computer science and physics and more than 130 US patents in the area of computer design and architecture.


Gara received his PhD in physics from the University of Wisconsin, Madison in 1987 for his work calculating the meson mass spectra utilizing a relativistic Bethe-Salpeter approach.

Industry Panel (Saturday, November 11, 2017 12:15-12:50 p.m.)

James Reinders (Moderator)

HPC Enthusiast & Consultant

James Reinders likes fast computers and the software tools to make them speedy.  More than 30 years in High Performance Computing (HPC) and Parallel Computing. 27 Years at Intel Corporation (retired June 2016). James is an author of eight books in the HPC field, numerous papers and blogs.

Peter Boyle

Professor, School of Physics and Astronomy, University of Edinburgh, and Co-Design Leader for The Allan Turing Institute

Prof. Boyle has worked in computational theoretical physics, and in particular in Lattice QCD and codesign since 1994, publishing more than 120 scientific papers. He has developed two supercomputer architectures in collaborations comprising Columbia University, Edinburgh University and IBM Research. His paper about the special purpose QCDOC computer was a Gordon Bell Prize Finalist at Supercomputing 2004. Prof. Boyle also designed the Level 1 Prefetch engine for the BlueGene/Q compute ASIC, resulting in papers that won the 2012 Gauss award, and a Gordon Bell Prize finalist paper with Lawrence Livermore National Laboratory in Supercomputing 2013. Prof. Boyle coauthored 5 US Patents with IBM on the BlueGene/Q design. Prof Boyle has been the principal investigator for an Intel Parallel Computing Centre since 2014 with an interest in many-core architectures and became the Codesign Leader for the Alan Turing Institute and Intel Strategic Partnership in 2016. Prof. Boyle is an Alan Turing Fellow, a Wolfson Fellow and has a part time affiliation with Brookhaven National Laboratory.

Dr. Barbara Chapman

Professor of Applied Mathematics & Statistics and Computer Science at Stony Brook University

Dr. Chapman is a Professor of Applied Mathematics and Statistics, and of Computer Science, at Stony Brook University, where she is affiliated with the Institute for Advanced Computational Science.  She also directs Computer Science and Mathematics Research at Brookhaven National Laboratory. She has performed research on parallel programming interfaces and the related implementation technology for over 20 years and has been involved in several efforts to develop community standards for parallel programming, including OpenMP, OpenACC and OpenSHMEM.  Her research group created the OpenUH compiler that enabled practical experimentation with proposed enhancements to application programming interfaces and the corresponding implementation techniques. This work considered features that enable parallelization of both Fortran and C programming languages. Her group moreover created a reference implementation of the library-based OpenSHMEM standard. Dr. Chapman has co-authored over 200 papers and two books. She obtained a B.Sc. with 1st Class Honours in Mathematics from the University of Canterbury and a Ph.D. in Computer Science from Queen’s University of Belfast.

Mike Dewar

Chief Technical Officer, NAG Group

As Chief Technical Officer, Mike is responsible for setting technical strategies and implementing technical work programmes for the NAG Group of Companies. As part of this role he manages NAG's Development Division with staff in Oxford, Manchester, Tokyo and Houston, which designs and implements the NAG family of products and delivers a range of technical services to customers. He is responsible for managing NAG's worldwide programme of technical collaboration, and maintains a watching brief on new and emerging technologies. Mike joined NAG in 1994, originally to manage the development of the Axiom computer algebra system, and has since worked in a variety of areas within the company. He led a number of EU-funded projects which developed technology which now underpins NAG's algorithmic repository ("the NAG engine"). More recently he has led a number of major HPC services engagements with customers throughout the world. Before joining NAG Mike was a lecturer in Computer Science at the University of Bath. Mike holds a first class honours degree in Mathematics and Computational Science from the University of St. Andrews, and a PhD from the University of Bath for his thesis “Interfacing Algebraic and Numeric Computation”.

Henry Gabb

Senior Principal Engineer in the Developer Products Division of the Intel Software and Services Group

Henry Gabb is a Senior Principal Engineer in the Developer Products Division of the Intel Software and Services Group. He first joined Intel in 2000 to help drive parallel computing in various application domains. He is the current editor of The Parallel Universe, Intel’s quarterly magazine devoted to software innovation. Prior to joining Intel, Henry was Director of Scientific Computing at the ERDC MSRC, a Department of Defense high-performance computing research center. His academic background is in the computational life sciences. Henry was a Research Fellow at the Imperial Cancer Research Fund (now part of Cancer Research UK) in London where he developed algorithms to predict the binding geometries of biomolecules. He did his postdoctoral research at l’Institut de Biologie et Physico-Chimique in Paris where he studied conformational transitions in nucleic acids. He holds a BS in biochemistry from Louisiana State University, an MS in medical informatics from the Northwestern Feinberg School of Medicine, and a PhD in molecular genetics from the University of Alabama at Birmingham School of Medicine. He has published extensively in computational life science and high-performance computing. Henry recently rejoined Intel after spending four years working on a second PhD in information science at the University of Illinois at Urbana-Champaign, where he applied informatics and machine learning to problems in healthcare and environmental chemical exposure.

Plenary Session (Saturday, November 11, 2017 4:30-5:30 p.m.)

Joshua L. Willis

Ph.D., Computational Scientist, California Institute of Technology, the LIGO Laboratory

Dr. Willis is a computational scientist at the California Institute of Technology, working for the LIGO Laboratory. He is also an associate professor of engineering and physics at Abilene Christian University, and has been a visiting senior scientist at the Max Planck Institute for Gravitational Physics every year since 2011. He has been a key developer of the PyCBC matched-filter pipeline that played a crucial role in each of LIGO's detections to date, and has been a part of the LIGO computing optimization team since 2014. He received bachelor's degrees in physics and mathematics from Abilene Christian, a master's in applied study in mathematics from Cambridge, and a doctorate in physics from Penn State University.

Dan Stanzione

Executive Director of the Texas Advanced Computing Center (TACC) at The University of Texas at Austin PHOTO NEEDED

Dr. Stanzione is the Executive Director of the Texas Advanced Computing Center (TACC) at The University of Texas at Austin since July 2014, previously serving as Deputy Director. He is the principal investigator (PI) for a National Science Foundation (NSF) grant to deploy and support Stampede2, a large scale supercomputer, which will have over twice the system performance of TACC’s original Stampede system. Stanzione is also the PI of TACC's Wrangler system, a supercomputer for data-focused applications. For six years he was co-director of CyVerse, a large-scale NSF life sciences cyberinfrastructure. Stanzione was also a co-principal investigator for TACC's Ranger and Lonestar supercomputers, large-scale NSF systems previously deployed at UT Austin. Stanzione received his bachelor's degree in electrical engineering and his master's degree and doctorate in computer engineering from Clemson University.

Plenary Session (Sunday, November 12, 2017 8:30-9:30 a.m.)

Prabhat 

Director of the Big Data Center at NERSC 

Prabhat leads the Data and Analytics Services team at NERSC. In this role, he is responsible for deploying the Big Data stack on NERSC platforms, spanning capability areas in Data Analytics, Management, Workflows, Visualization, Transfer and Access. Prabhat is the Director of the Big Data Center at NERSC, which is enabling capability Data applications to run on the Cori supercomputer. Prabhat’s current research interests span Deep Learning, Machine Learning and Applied Statistics. Prabhat received an ScM in Computer Science from Brown University (2001) and a B.Tech in Computer Science and Engineering from IIT-Delhi (1999). He is currently pursuing a PhD in the Earth and Planetary Sciences Department at U.C. Berkeley.

Michael F. Wehner

Senior Staff Scientist in the Computational Research Division at the Lawrence Berkeley National Laboratory

Michael F. Wehner is a senior staff scientist in the Computational Research Division at the Lawrence Berkeley National Laboratory. Dr. Wehner’s current research concerns the behavior of extreme weather events in a changing climate, especially heat waves, intense precipitation, drought and tropical cyclones. Before joining the Berkeley Lab in 2002, Wehner was an analyst at the Lawrence Livermore National Laboratory in the Program for Climate Modeling Diagnosis and Intercomparison. He is the author or co-author of over 165 scientific papers and reports. He was a lead author for both the 2013 Fifth Assessment Report of the Intergovernmental Panel on Climate Change and the 2nd,3rd and 4th US National Assessments on climate change. Dr. Wehner earned his master’s degree and Ph.D. in nuclear engineering from the University of Wisconsin-Madison, and his bachelor’s degree in Physics from the University of Delaware.

Plenary Session (Sunday, November 12, 2017 12:15-1:30 p.m.) 

Jim Held

Ph.D., Intel Fellow & Director Emerging Technologies Research, Intel Labs

Jim Held leads Intel Labs emerging technology research, developing hardware and software technologies for future microprocessors and platforms. He co-leads Intel’s quantum computing research. Since joining Intel in 1990, Held has served in a variety of positions in Intel Labs, leading organizations and virtual teams conducting research in microprocessor and platform architecture, parallel computing, interconnect technology, multimedia, computer-supported collaboration and IA-based signal processing. Held earned a Ph.D. (1988) in Computer and Information Science, from the University of Minnesota.

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