Completing a successful software conversion to Intel® architecture from either Acorn RISC Machine* (ARM) or PowerPC* (PPC) requires an awareness of architecture differences and the subsequent impact to the software when migrating. The steps below (1-3) outline the information that should be considered when planning a software product port from either ARM or PPC to Intel® architecture-based platforms.
Goal: Ensure the SW executes correctly on current platform using the target OS.
Guidance: Since this step ensures stability of the same code running on the target OS, do not make other software design changes in this step. If the target solution will use an SMP OS, then this step should use the SMP version of the target OS, regardless of the number of cores that are enabled on the current platform.
1.1. Will an in-house OS need to be ported to Intel architecture?
1.2. Install new OS on current platform and compile/install all code for the new OS.
1.3. Run required tests to ensure the SW executes correctly on current platform running the new OS.
Goal: Successfully initialize and boot the system to the OS, and execute the entire SW stack correctly on the Intel architecture target platform.
Guidance: Restrict the execution to one core by configuring the firmware to use one core. This restriction will simplify this step by eliminating the possibility for multi-core complications, and focus only on correct execution of the code.
References: IBV Solutions and Services, IA Boot Loader Development, Intel Architecture Instruction Set, Architecture Specific Differences, Vector Oriented Code, Endianness, Software Development Tools, Architecture Migration Tools, Intel Chipset Drivers.
2.1. Initialize the system: Do you prefer to adopt a BIOS or develop a custom Intel architecture boot loader?
2.2. Survey and Install OS related code:
2.3. Port assembly code: Any assembly code will need to be translated or rewritten for Intel Architeture.
2.4. Are vector oriented instructions used?
2.5. Does the in-house code abstract the endian architecture of the processor?
2.6. Refer to Architecture Specific Differences to determine if any other changes are required.
2.7. Build, test, and debug the code until it executes correctly on one Intel architecture core.
Goal: Ensure the efficiency of the serial code (power and performance).
Guidance: Serial code must be optimized before multi-core design changes and optimization is performed. Understand the power and performance requirements and establish a baseline before making any changes. Refer to these books for tuning methodologies, tools, and performance libraries (TBD). Create a baseline, and make only one change at a time.
Collateral: Refer to Power and Performance Tuning, Software Development Tools.
3.1. Analyze performance:
3.2. Generate alternatives and implement code changes:
3.3. Build, test, and debug the change.
3.4. Optimization is a reiterative process. Go back to step 3.1 and cycle through again.