Port Software to Intel Architecture

Porting Software

Completing a successful software conversion to Intel® architecture from either Acorn RISC Machine* (ARM) or PowerPC* (PPC) requires an awareness of architecture differences and the subsequent impact to the software when migrating. The steps below (1-3) outline the information that should be considered when planning a software product port from either ARM or PPC to Intel® architecture-based platforms.

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Step 1: Port Code to Target OS 

Goal:   Ensure the SW executes correctly on current platform using the target OS.

Guidance:   Since this step ensures stability of the same code running on the target OS, do not make other software design changes in this step. If the target solution will use an SMP OS, then this step should use the SMP version of the target OS, regardless of the number of cores that are enabled on the current platform.

References:   Refer to Operating System Abstraction Layer, Porting

Step 1 Flow:

1.1. Will an in-house OS need to be ported to Intel architecture?

1.2. Install new OS on current platform and compile/install all code for the new OS.

  • If any TPV drivers, libraries, or middleware SW is required, check with TPV to get the new OS equivalents. (Will also need to check for Intel architecture equivalents in step 2.2)

1.3. Run required tests to ensure the SW executes correctly on current platform running the new OS.

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Step 2: Execute the Code Correctly on One IA Core 

Goal: Successfully initialize and boot the system to the OS, and execute the entire SW stack correctly on the Intel architecture target platform.

Guidance: Restrict the execution to one core by configuring the firmware to use one core. This restriction  will simplify this step by eliminating the possibility for multi-core complications, and focus only on correct execution of the code.

References: IBV Solutions and Services, IA Boot Loader Development, Intel Architecture Instruction Set, Architecture Specific Differences, Vector Oriented Code, Endianness, Software Development Tools, Architecture Migration Tools, Intel Chipset Drivers.

Step 2 Flow:

2.1. Initialize the system: Do you prefer to adopt a BIOS or develop a custom Intel architecture boot loader?

2.2. Survey and Install OS related code:

  • Check with TPVs to get  Intel architecture equivalents of any required third party drivers, libraries, middleware, and tools. In-house drivers and libraries will need to be manually ported.
  • If graphics or video is required, refer to Intel Graphics Drivers.
  • Refer to Intel Chipset Drivers for Intel embedded chipset drivers.
  • Contact your Intel embedded support representative for the latest Windows platform chipset driver packages or for help finding a specific driver.

2.3. Port assembly code: Any assembly code will need to be translated or rewritten for Intel Architeture.

2.4. Are vector oriented instructions used?

2.5. Does the in-house code abstract the endian architecture of the processor?

  • Yes:   The code is endian-neutral. No changes are required.
  • No:    Refer to Endianness information as a guide to update the code for endian-neutral or little-endian memory architecture. If a large amount of big-endian code exists, consider using the Intel Intel Bi-Endian Compiler (BEC).

2.6. Refer to Architecture Specific Differences to determine if any other changes are required.

2.7. Build, test, and debug the code until it executes correctly on one Intel architecture core.

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Step 3: Optimize for  Power and Performance on One IA Core 

Goal:   Ensure the efficiency of the serial code (power and performance).

Guidance:   Serial code must be optimized before multi-core design changes and optimization is performed. Understand the power and performance requirements and establish a baseline before making any changes. Refer to these books for tuning methodologies, tools, and performance libraries (TBD). Create a baseline, and make only one change at a time.

Collateral:   Refer to Power and Performance Tuning, Software Development Tools.

Step 3 Flow:

3.1. Analyze performance:

  • Measure the results and compare against the baseline. Stop making changes when the performance requirements are achieved.
  • Use performance analyzers to pinpoint hotspots and thread profilers to identify thread imbalances for multithreaded designs.

3.2. Generate alternatives and implement code changes:

  • For advanced optimizations, use compiler features such as Intel C++ Compiler Profile Guide Optimization (PGO), for executable size and power consumption.
  • Update libraries and drivers before application changes:
    • Use Intel Performance Libraries or other  performance libraries enabled for IA to increase performance with a variety of APIs that are highly tuned for IA. Functions include: video, imaging, compression, cryptography, audio, speech recognition, and signal processing and code component functions.

3.3. Build, test, and debug the change.

3.4. Optimization is a reiterative process. Go back to step 3.1 and cycle through again.