Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

ID 823097
Date 1/27/2025
Public
Document Table of Contents

1. Terms and Acronyms

Updated for:
Intel® Quartus® Prime Design Suite 24.3.1
IP Version 1.1.3
Table 1.  Terms and Acronyms
Term Definition
PCIe Peripheral Component Interconnect Express (PCI Express)
DMA Direct Memory Access
MCDMA Multi-Channel Direct Memory Access
IP Intellectual Property
HIP Hard IP
SS Subsystem
SS2APP PCIE Subsystem to Application
APP2SS Application to PCIe Subsystem
H2D Host to Device
D2H Device to Host
CSR Control Status Register
PD Packet Descriptor
QID Queue Identification
TIDX Queue Extract Index (Pointer)
HIDX Queue Insert Index (Pointer)
TLP Transaction Layer Protocol
MPS Maximum Payload Size
MRRS Maximum Read Request Size
PBA Pending Bit Array
API Application Programming Interface
AXI-4 Advanced eXtensible Interface associated with AMBA version 4.0
AXI-ST AXI Streaming
SOP Start of a Packet (or File) for streaming
EOP End of a Packet (or File) for streaming

File (or Packet)

A group of descriptors defined by SOP and EOP bits of the descriptor for the streaming. At AXI-ST user interface , a file (or packet) is marked by means of TUSER.SOP (Optional for SOP) and TLAST (as EOP). At Avalon streaming user interface, a file (or packet) is marked by means of SOP/EOP.
BAM Bursting Manager
BAS Bursting Subordinate
CEB Configuration Extension Bus
MSI Message Signaled Interrupt
MSI-X Message Signaled Interrupt - Extended
FLR Function Level Reset
ATT Address Translation Table
DPDK Data Path Development Kit
SR-IOV Single Root I/O Virtualization
PMD Poll Mode Driver
PF Physical Function
VF Virtual Function
HPS Hard Processor System
SoC System on Chip
QOS Quality of Service