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3.1.1.1. PCIe* TLP Constructor
3.1.1.2. PCIe* TLP ID Generation
3.1.1.3. PCIe TX Credit Controller
3.1.1.4. PCIe* TX Scheduler
3.1.1.5. PCIe TLP Completer
3.1.1.6. PCIe RX Router
3.1.1.7. PCIe* MSI-X Controller
3.1.1.8. PCIe BAR0
3.1.1.9. PCIe Bursting Manager (BAM)
3.1.1.10. Completion Timeout Parser
3.1.1.11. Control Shadow Parser
4.2.1. Application Packet Receive Interface
4.2.2. Application Packet Transmit Interface
4.2.3. Control Shadow Interface
4.2.4. Transmit Flow Control Credit Interface
4.2.5. Completion Timeout Interface
4.2.6. PCIe* Miscellaneous Signals
4.2.7. Control and Status Register Responder Manager Interface
4.2.8. Bursting Manager Interface
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1. Terms and Acronyms
Updated for: |
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Intel® Quartus® Prime Design Suite 24.3.1 |
IP Version 1.1.3 |
Term | Definition |
---|---|
PCIe | Peripheral Component Interconnect Express (PCI Express) |
DMA | Direct Memory Access |
MCDMA | Multi-Channel Direct Memory Access |
IP | Intellectual Property |
HIP | Hard IP |
SS | Subsystem |
SS2APP | PCIE Subsystem to Application |
APP2SS | Application to PCIe Subsystem |
H2D | Host to Device |
D2H | Device to Host |
CSR | Control Status Register |
PD | Packet Descriptor |
QID | Queue Identification |
TIDX | Queue Extract Index (Pointer) |
HIDX | Queue Insert Index (Pointer) |
TLP | Transaction Layer Protocol |
MPS | Maximum Payload Size |
MRRS | Maximum Read Request Size |
PBA | Pending Bit Array |
API | Application Programming Interface |
AXI-4 | Advanced eXtensible Interface associated with AMBA version 4.0 |
AXI-ST | AXI Streaming |
SOP | Start of a Packet (or File) for streaming |
EOP | End of a Packet (or File) for streaming |
File (or Packet) |
A group of descriptors defined by SOP and EOP bits of the descriptor for the streaming. At AXI-ST user interface , a file (or packet) is marked by means of TUSER.SOP (Optional for SOP) and TLAST (as EOP). At Avalon streaming user interface, a file (or packet) is marked by means of SOP/EOP. |
BAM | Bursting Manager |
BAS | Bursting Subordinate |
CEB | Configuration Extension Bus |
MSI | Message Signaled Interrupt |
MSI-X | Message Signaled Interrupt - Extended |
FLR | Function Level Reset |
ATT | Address Translation Table |
DPDK | Data Path Development Kit |
SR-IOV | Single Root I/O Virtualization |
PMD | Poll Mode Driver |
PF | Physical Function |
VF | Virtual Function |
HPS | Hard Processor System |
SoC | System on Chip |
QOS | Quality of Service |