Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

Download PDF
ID 823097
Date 1/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Functional Description 4. Interfaces 5. HAL Driver for DMA SoC Mode  6. Parameters 7. Registers 8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide
2. Introduction x
2.1. Device Family Support 2.2. Release Information 2.3. Resource Utilization
3. Functional Description x
3.1. DMA PCIe* Mode 3.2. DMA SoC Mode 3.3. Device Port 3.4. Prefetcher Engine 3.5. DMA Arbiter 3.6. DMA Router 3.7. CSRUnit 3.8. Descriptor Handling 3.9. Interrupts 3.10. Reset Initialization Flows 3.11. Transaction Flow
3.1. DMA PCIe* Mode x
3.1.1. Submodules
3.1.1. Submodules x
3.1.1.1. PCIe* TLP Constructor 3.1.1.2. PCIe* TLP ID Generation 3.1.1.3. PCIe TX Credit Controller 3.1.1.4. PCIe* TX Scheduler 3.1.1.5. PCIe TLP Completer 3.1.1.6. PCIe RX Router 3.1.1.7. PCIe* MSI-X Controller 3.1.1.8. PCIe BAR0 3.1.1.9. PCIe Bursting Manager (BAM) 3.1.1.10. Completion Timeout Parser 3.1.1.11. Control Shadow Parser
3.2. DMA SoC Mode x
3.2.1. Interrupt Controller 3.2.2. Host AXI-4 Agent 3.2.3. Host CSR AXI-4 Lite Agent
3.3. Device Port x
3.3.1. ST Source Agent/ST Sink Agent/MM Agent 3.3.2. Descriptor Engine 3.3.3. Agent Controller 3.3.4. Constructor 3.3.5. Responder 3.3.6. Width Adaptation FIFO
3.8. Descriptor Handling x
3.8.1. Link Descriptor 3.8.2. Data Descriptor 3.8.3. Responder Descriptor 3.8.4. Descriptor Chain 3.8.5. Aligned and Unaligned Transfer Support
3.8.2. Data Descriptor x
3.8.2.1. Data Descriptor - H2D Streaming Transfer 3.8.2.2. Data Descriptor - D2H Streaming Transfer 3.8.2.3. Data Descriptor - H2D Memory Transfer
3.8.3. Responder Descriptor x
3.8.3.1. Responder Descriptor - H2D Streaming Transfer 3.8.3.2. Responder Descriptor - D2H Streaming Transfer 3.8.3.3. Responder Descriptor - H2D Memory Transfer
3.8.4. Descriptor Chain x
3.8.4.1. Descriptor Fetch and Status Update Mechanism
3.11. Transaction Flow x
3.11.1. General DMA Operation Flow 3.11.2. Host to Device (H2D) Flow 3.11.3. Device to Host (D2H) Flow 3.11.4. Soft Reset Handshake Flow
4. Interfaces x
4.1. Port List 4.2. DMA PCIe* Mode Interfaces 4.3. DMA SoC Mode Interfaces 4.4. Device Port Interfaces 4.5. Resets 4.6. Clocks
4.2. DMA PCIe* Mode Interfaces x
4.2.1. Application Packet Receive Interface 4.2.2. Application Packet Transmit Interface 4.2.3. Control Shadow Interface 4.2.4. Transmit Flow Control Credit Interface 4.2.5. Completion Timeout Interface 4.2.6. PCIe* Miscellaneous Signals 4.2.7. Control and Status Register Responder Manager Interface 4.2.8. Bursting Manager Interface
4.3. DMA SoC Mode Interfaces x
4.3.1. Host AXI-4 Memory Map Manager Interface 4.3.2. Host AXI-4 Lite CSR Memory Map Subordinate Interface 4.3.3. Interrupt Interface
4.4. Device Port Interfaces x
4.4.1. Device to Host <PORT#> AXI-ST Subordinate Interface 4.4.2. Device to Host <PORT#> Avalon-ST Sink Interface 4.4.3. Host to Device <PORT#> AXI-ST Manager Interface 4.4.4. Host to Device <PORT#> Avalon-ST Source Interface 4.4.5. Host to Device <PORT#> AXI-4 Manager Interface
5. HAL Driver for DMA SoC Mode  x
5.1. Descriptor Indexing  5.2. HAL Public API 
5.1. Descriptor Indexing  x
5.1.1. Data Descriptors  5.1.2. Responders  Responder wrap around
5.2. HAL Public API  x
5.2.1. Software Features 5.2.2. intel_ssgdma.c  5.2.3. intel_ssgdma_global.c 5.2.4. intel_ssgdma_device_port.c  5.2.5. intel_ssgdma_descriptor.c 
6. Parameters x
6.1. DMA Settings 6.2. Device Port Settings 6.3. DMA PCIe Mode Settings 6.4. DMA SoC Mode Settings 6.5. Example Design
6.2. Device Port Settings x
6.2.1. H2D MM 6.2.2. H2D ST 6.2.3. D2H ST
7. Registers x
7.1. Global CSR 7.2. MSI-X Memory Space 7.3. Device Port Control Register
1. Terms and Acronyms
2. Introduction
3. Functional Description
4. Interfaces
5. HAL Driver for DMA SoC Mode 
6. Parameters
7. Registers
8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

5.1.2. Responders 

Responders are also stored in the host memory as an array. The IP writes to the responder array, when writeback mode is enabled. However, the link descriptors do not have a responder. Hence, the responder array is not “in sync” with the descriptor array. 

Q_SIZE and Q_RESP_SIZE = 2
Table 64.  Descriptors  
 sw_idx Description  hw_idx
Block 1

0 

Link Descriptor 

1 

1 

Data Descriptor 1 

2 

2 

Data Descriptor 2 

3 

<n> 

Data Descriptor <n>

<n+1> 

127 

Data Descriptor 127 

128 
Block 2 

128 

Data Descriptor 128

129 

129 

Data Descriptor 129

130 

<n> 

Data Descriptor <n>

<n+1> 

255 

Data Descriptor 255 

256 
Table 65.  Responders
 sw_idx Description  hw_idx
Block 1

0 

Responder 1 

2 

1 

 Responder 2

3 

2 

 Responder 3 4

<n> 

Responder <n+1>

<n+2> 
125 Responder 126 127
126 Responder 127 128

127 

 Responder 128

130 
Block 2 

128 

Responder 129

131 

129 

 Responder 130

132 
130 Responder 131 133

<n> 

Responder <n+1>

<n+2> 
252 Responder 253 255
253 Responder 254 256
254 Responder 255 2

255 

 Responder 256

3 

The driver also provides a responder tracking index (sw_extract_hw_idx). This index ensures that all responders are evaluated by the software. 

Responder wrap around

The sw_idx cannot be derived from hw_idx when the responder wrap around occurs, because within the responder array, there is the same hardware index. To solve this, the driver must have a responder counter(resp_ptr_act_idx) to track the completed responder. 

This counter counts each time a responder is completed and is equivalent to sw_idx. 

Responder block size = 1, with 3 rounds of wrap around.
Software IDX   1st Round 2nd Round 3rd Round
Hardware IDX Hardware IDX Hardware IDX
0 Responder 1 2 3 4
1 Responder 2 3 4 5
2 Responder 3 4 5 6
<n> Responder <n+1> <n+2> <n+3> <n+4>
125 Responder 126 127 128 2
126 Responder 127 128 2 3
127 Responder 128 2 3 4
 

The driver uses another counter(resp_ptr_tmp_idx) to back trace the responder. 

To update this value, call intel_ssgdma_set_resp_ptr_tmp_idx. The input previous_n_resp represents the previously completed responder(resp_ptr_tmp). It can be retrieved from intel_ssgdma_complete_callback or intel_ssgdma_device_port_poll_for_completion. To move to the next resp_ptr_tmp, use intel_ssgdma_get_next_tmp_resp, as this function deals with the wrap around of the responder buffer. 

Level Two Title