Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

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ID 823097
Date 1/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Functional Description 4. Interfaces 5. HAL Driver for DMA SoC Mode  6. Parameters 7. Registers 8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide
2. Introduction x
2.1. Device Family Support 2.2. Release Information 2.3. Resource Utilization
3. Functional Description x
3.1. DMA PCIe* Mode 3.2. DMA SoC Mode 3.3. Device Port 3.4. Prefetcher Engine 3.5. DMA Arbiter 3.6. DMA Router 3.7. CSRUnit 3.8. Descriptor Handling 3.9. Interrupts 3.10. Reset Initialization Flows 3.11. Transaction Flow
3.1. DMA PCIe* Mode x
3.1.1. Submodules
3.1.1. Submodules x
3.1.1.1. PCIe* TLP Constructor 3.1.1.2. PCIe* TLP ID Generation 3.1.1.3. PCIe TX Credit Controller 3.1.1.4. PCIe* TX Scheduler 3.1.1.5. PCIe TLP Completer 3.1.1.6. PCIe RX Router 3.1.1.7. PCIe* MSI-X Controller 3.1.1.8. PCIe BAR0 3.1.1.9. PCIe Bursting Manager (BAM) 3.1.1.10. Completion Timeout Parser 3.1.1.11. Control Shadow Parser
3.2. DMA SoC Mode x
3.2.1. Interrupt Controller 3.2.2. Host AXI-4 Agent 3.2.3. Host CSR AXI-4 Lite Agent
3.3. Device Port x
3.3.1. ST Source Agent/ST Sink Agent/MM Agent 3.3.2. Descriptor Engine 3.3.3. Agent Controller 3.3.4. Constructor 3.3.5. Responder 3.3.6. Width Adaptation FIFO
3.8. Descriptor Handling x
3.8.1. Link Descriptor 3.8.2. Data Descriptor 3.8.3. Responder Descriptor 3.8.4. Descriptor Chain 3.8.5. Aligned and Unaligned Transfer Support
3.8.2. Data Descriptor x
3.8.2.1. Data Descriptor - H2D Streaming Transfer 3.8.2.2. Data Descriptor - D2H Streaming Transfer 3.8.2.3. Data Descriptor - H2D Memory Transfer
3.8.3. Responder Descriptor x
3.8.3.1. Responder Descriptor - H2D Streaming Transfer 3.8.3.2. Responder Descriptor - D2H Streaming Transfer 3.8.3.3. Responder Descriptor - H2D Memory Transfer
3.8.4. Descriptor Chain x
3.8.4.1. Descriptor Fetch and Status Update Mechanism
3.11. Transaction Flow x
3.11.1. General DMA Operation Flow 3.11.2. Host to Device (H2D) Flow 3.11.3. Device to Host (D2H) Flow 3.11.4. Soft Reset Handshake Flow
4. Interfaces x
4.1. Port List 4.2. DMA PCIe* Mode Interfaces 4.3. DMA SoC Mode Interfaces 4.4. Device Port Interfaces 4.5. Resets 4.6. Clocks
4.2. DMA PCIe* Mode Interfaces x
4.2.1. Application Packet Receive Interface 4.2.2. Application Packet Transmit Interface 4.2.3. Control Shadow Interface 4.2.4. Transmit Flow Control Credit Interface 4.2.5. Completion Timeout Interface 4.2.6. PCIe* Miscellaneous Signals 4.2.7. Control and Status Register Responder Manager Interface 4.2.8. Bursting Manager Interface
4.3. DMA SoC Mode Interfaces x
4.3.1. Host AXI-4 Memory Map Manager Interface 4.3.2. Host AXI-4 Lite CSR Memory Map Subordinate Interface 4.3.3. Interrupt Interface
4.4. Device Port Interfaces x
4.4.1. Device to Host <PORT#> AXI-ST Subordinate Interface 4.4.2. Device to Host <PORT#> Avalon-ST Sink Interface 4.4.3. Host to Device <PORT#> AXI-ST Manager Interface 4.4.4. Host to Device <PORT#> Avalon-ST Source Interface 4.4.5. Host to Device <PORT#> AXI-4 Manager Interface
5. HAL Driver for DMA SoC Mode  x
5.1. Descriptor Indexing  5.2. HAL Public API 
5.1. Descriptor Indexing  x
5.1.1. Data Descriptors  5.1.2. Responders 
5.2. HAL Public API  x
5.2.1. Software Features 5.2.2. intel_ssgdma.c  5.2.3. intel_ssgdma_global.c 5.2.4. intel_ssgdma_device_port.c  5.2.5. intel_ssgdma_descriptor.c 
6. Parameters x
6.1. DMA Settings 6.2. Device Port Settings 6.3. DMA PCIe Mode Settings 6.4. DMA SoC Mode Settings 6.5. Example Design
6.2. Device Port Settings x
6.2.1. H2D MM 6.2.2. H2D ST 6.2.3. D2H ST
7. Registers x
7.1. Global CSR 7.2. MSI-X Memory Space 7.3. Device Port Control Register
1. Terms and Acronyms
2. Introduction
3. Functional Description
4. Interfaces
5. HAL Driver for DMA SoC Mode 
6. Parameters
7. Registers
8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

7.1. Global CSR

The space contains global control/status registers that control the SSGDMA operation.

Table 124.  Global CSR (GSR) Register Map
Register Name Address Offset Access Type Description
Reserved 0x0-0xFF RO Reserved.
CTRL 0x100 R/W/W1S/RO Control registers.
STATUS 0x104 R/W/W1C/RO Status registers.
WB_INTR_TIMEOUT 0x108 R/W/RO Delay the completion writeback and the interrupt until the time elapsed from a prior writeback/interrupt exceeds the delay value in this register.
VER_NUM 0x10C RO SSGDMA IP version number.
Reserved 0x110 RO Reserved.
WATCHDOG_TIMEOUT 0x114 R/W/RO The watchdog timer in SSGDMA IP in the event of non-responding transaction incident happened.
SCRATCH 0X118 R/W Scratch register.
IP_PARAM1 0x11C RO The parameter settings configured during IP generation time.
DEVICE_PORTS_IRQ_STATUS 0x120 RO Provide and overview of the interrupt status (q_irq) of all H2D MM/H2D ST/D2H ST device ports. Applicable for DMA SoC mode only.
Reserved 0x124-0xF_FFFF RO Reserved.
Table 125.  CTRL (Offset 0x100)
Bit [31:0] Name R/W Access Default Description
[31:8] rsvd RO 0 Reserved.
[7:3] unused_gcsr_ctrl_field R/W 0 This field is set to 0. Write access to this field has no effect.
[2] watchdog_timer_en R/W 0 Enable the watchdog timer for non-responding transaction incident happened.
Note: You must configure this bit only during the initialization stage.
[1] run_prefetch_engine R/W1S 0

Enable the Prefetcher Engine to begin descriptor fetching operation.

This bit is cleared when hard reset is asserted.
[0] reset_prefetch_engine R/W1S 0

Reset the Prefetcher Engine. This bit is automatically cleared when the reset sequence has completed. Therefore, software need to poll for the status of this bit to be cleared by hardware to ensure the reset sequence has finished.

Once the reset sequence in the Prefetcher Engine completes, software is expected to reset each device port based on the reset sequence as described in reset initialization flow section.

You need to set the software to the run_prefetch_engine to begin descriptor fetching operation after the reset completion.
Note: W1S register attribute means the software can write 1 to set the field. There is no effect if the software writes 0 to this field.
Table 126.  STATUS (0x104)
Bit [31:0] Name R/W Access Default Description
[31] irq RO 0 Set when there is an interrupt asserted upon descriptor completion. This interrupt bit is set in the event of any q_irq bit assertion described in the Q_STATUS register from all device ports. The software should poll for the q_irq bits in all available device ports to identify the source of interrupt assertion and clearing them. Hardware automatically clears this irq bit if the software has cleared all q_irq bits in all available device ports.
Note: Applicable for DMA SoC mode only.
[30] watchdog_timeout_error R/W1C 0

Set when the watchdog timeout occurred due to a non-responding transaction in the SSGDMA IP.
[29:24] unused_gcsr_status_field R/W 0 This field is set to 0. Write access to this field has no effect.
[23:0] rsvd RO 0 Reserved.
Note: W1C register attribute means software can write 1 to clear the field. Writing 0 to this field has no effect.
Table 127.  WB_INTR_TIMEOUT ( 0x108)
Bit [31:0] Name R/W Access Default Description
[31:24] rsvd RO 0 Reserved.
[23:20] unused_gcsr_field R/W 0 This field is set to 0. Write access to this field has no effect.
[19:0] wb_intr_timeout R/W 0

Delay the interrupt until the time elapsed from a prior interrupt exceeds the delay value in this register. Each unit is 2ns.
Table 128.  VER_NUM (0x10C)
Bit [31:0] Name R/W Access Default Description
[31:24] rsvd RO 0 Reserved.
[23:16] MAJOR_VER RO 1 Major version number of SSGDMA IP.
[15:8] UPDATE_VER RO 1 Update version number of SSGDMA IP.
[7:0] PATCH_VER RO 3 Patch version number of SSGDMA IP.
Table 129.  WATCHDOG_TIMEOUT (0x114)
Bit [31:0] Name R/W Access Default Description
[19:0] watchdog_timeout R/W 0 The watchdog timer in SSGDMA IP in the event that a non-responding AXI4 transaction scenario happened. Each unit is 2ns.
[23:20] unused_gcsr_watchdog_field R/W 0 This field is set to 0. Write access to this field has no effect.
[31:24] rsvd RO 0 Reserved.
Table 130.  SCRATCH (0x118)
Bit [31:0] Name R/W Access Default Description
[31:0] scratch R/W 0 Scratch register for testing register read and write operations.
Table 131.  IP_PARAM (0x11C)
Bit [31:0] Name R/W Access Default Description
[31] unaligned_access_en RO Build time configured Unaligned addressing access support.
[30:26] num_d2h_st_ports RO Build time configured Number of D2H ST Device Port.
[25:21] num_h2d_st_ports RO Build time configured Number of H2D ST Device Port.
[20:16] num_h2d_mm_ports RO Build time configured Number of H2D MM Device Port.
[15:7] rsvd RO 0 Reserved.
[6] addr_64bits_en RO Build time configured DMA PCIe mode 64-bits address capability.
[5:4] pcie_func_mode RO Build time configured
  • PCIe operation mode.
  • 2'b00 - Native Endpoint.
  • 2'b01-2'b11 - Reserved.
[3:2] rsvd RO 0 Reserved.
[1:0] dma_mode RO Build time configured
  • SSGDMA operation mode.
  • 2'b00 - DMA PCIe mode.
  • 2'b01 - DMA SoC mode.
  • 2'b10 - 2'b11 - Reserved.
Table 132.  DEVICE_PORTS_IRQ_STATUS (0x120)
Bit [31:0] Name R/W Access Default Description
[31:16] rsvd RO 0 Reserved.
[15:0] device_ports_irq_status RO 0

Provide an overview of the interrupt status (q_irq) of all H2D MM/H2D ST/D2H ST device ports.

For example:
  • NUM_D2H_ST_PORTS = 1
  • NUM_H2D_ST_PORTS = 2
  • NUM_H2D_MM_PORTS = 3
The build time configured:
  • device_ports_irq_status [0] represents q_irq status of D2H ST device port 0
  • device_ports_irq_status [1] represents q_irq status of H2D ST device port 0
  • device_ports_irq_status [3] represents q_irq status of H2D MM device port 0
  • device_ports_irq_status [5] represents q_irq status of H2D MM device port 2
  • device_ports_irq_status [15:6] : N/A (default=0)
Note: Applicable for DMA SoC mode only. For DMA PCIe mode, the interrupt source is coming from MSI-X TLP to PCIe host.

Software should clear the corresponding q_irq. device_ports_irq_status allows read-only access for software because it reflects the value of each q_irq eventually.

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