MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 7/08/2024
Public
Document Table of Contents

4.2. Assigning the RZQ pin and Dedicated Reference Clock Pin for MIPI D-PHY IP

The MIPI D-PHY IP must use the dedicated RZQ pin for OCT calibration.

The RZQ pin must be placed at byte location 3 (at pin index 38) or byte location 5 (at pin index 62). You can select the RZQ pin location during IP generation. Look for the RZQ Pin parameter on the IP Configuration tab under the DPHY IP tab. Selecting RZQ 0 places the RZQ pin in byte location 3, while selecting RZQ 1 places the RZQ pin in byte location 5.

When an RZQ pin is used, you cannot use the remaining pin from the same BYTE location for MIPI D-PHY functions. For example, when placing the RZQ pin at pin index 62, you cannot use the remaining I/O pin on byte location 5 for the MIPI D-PHY IP. The RZQ pin must connect to a 240Ω onboard resistor. You cannot share the RZQ pin used for the MIPI D-PHY IP with an EMIF IP from the same I/O bank.

You must assign the MIPI D-PHY IP reference clock pin to a dedicated reference clock pin. To optimize the pin assignment, you can place the MIPI D-PHY IP reference clock pin and RZQ pin from the same byte location. For example, for an RZQ pin at index 62, you can use the dedicated clock pins at pin index locations 61 and 60 for the reference clock pins for MIPI D-PHY IP.

You can configure the reference clock pin I/O standard as LVCMOS or true differential signaling at the same VCCIO_PIO level. The I/O standard assignment is available in the MIPI D-PHY IP GUI. For a reference clock with a true differential signaling I/O standard, you cannot use the remaining pin from the same BYTE location for MIPI D-PHY functions. You can place the reference clock pins in the same byte location as the RZQ pin. For a reference clock with an LVCMOS I/O standard, you can use the remaining pin from the same BYTE location for MIPI D-PHY functions.