External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions

The mailbox is a software structure that the calibration subsystem manager (SSM) polls periodically.

All accesses to the mailbox should align to 32-bit boundaries, with no byte masking support. The following tables show the mailbox structure and the calibration status register definition.

Table 19.  Mailbox Structure
Register Name Byte Offset Width (bits) Access Description
STATUS 1024 32 RO

[Output] Status Register

“At a Glance” status register. This field is automatically updated by the Calibration I/O SSM and no explicit operation is required to trigger an update.
Reserved
CMD_PARAM_6 1056 32 RW [Input] This register specifies the seventh parameter (if applicable) for the requested command.
CMD_PARAM_5 1060 32 RW [Input] This register specifies the sixth parameter (if applicable) for the requested command.
CMD_PARAM_4 1064 32 RW [Input] This register specifies the fifth parameter (if applicable) for the requested command.
CMD_PARAM_3 1068 32 RW [Input] This register specifies the fourth parameter (if applicable) for the requested command.
CMD_PARAM_2 1072 32 RW [Input] This register specifies the third parameter (if applicable) for the requested command.
CMD_PARAM_1 1076 32 RW [Input] This register specifies the second parameter (if applicable) for the requested command.
CMD_PARAM_0 1080 32 RW [Input] This register specifies the first parameter (if applicable) for the requested command.
CMD_REQ 1084 32 RW [Input] This register specifies the command to be performed and the target IP type and identifier.
Reserved
CMD_RESPONSE_DATA_2 1104 32 RO [Output] For commands that return up to 3.5x 32-bit values, CMD_RESPONSE_DATA 0/1/2, and/or CMD_RESPONSE_DATA_SHORT fields contain the requested response data.
CMD_RESPONSE_DATA_1 1108 32 RO

[Output] This register can contain two types of values depending on the requested operation.

For commands that return up to 3.5x 32-bit values, CMD_RESPONSE_DATA 0/1/2, and/or CMD_RESPONSE_DATA_SHORT fields contain the requested response data.

For commands that return more data, this register specifies a pointer to a data buffer within the 4K User. It is a byte offset relative to the start of the 4Kbyte RAM. Do not assume that this offset value remains static as the value of this pointer offset may change depending on the requested operation.
CMD_RESPONSE_DATA_0 1112 32 RO

[Output] This register can contain two types of values depending on the requested operation.

For commands that return up to 3.5x 32-bit values, CMD_RESPONSE_DATA 0/1/2, and/or CMD_RESPONSE_DATA_SHORT fields contain the requested response data.

For commands that return more data, this value contains the size of the returned data structure in bytes. The location of the data buffer is specified in CMD_RESPONSE_DATA_1.
CMD_RESPONSE_STATUS 1116 32 RW

[Output] Command Interface status

Captures the current state of the Mailbox’s Command Interface (that is, Is the response data ready?). CMD_RESPONSE_DATA_SHORT field in this register can be used for 16-bit response data.
Table 20.  Calibration Status Register
Bit Name Description Access Reset
[31:3] Reserved
[2] STATUS_CAL_BUSY

Indicates calibration busy status of any external memory interfaces in the IO96:

'1' - One or more EMIF instances are busy with calibration.

'0' - No EMIF instances are busy with calibration.
RO 0x0
[1] STATUS_CAL_FAIL

Indicates calibration failure status of any external memory interfaces in the IO96:

'1' - One or more EMIF instances have failed to calibrate successfully.

'0' - No calibration failures have been reported for any of the EMIFs.
RO 0x0
[0] STATUS_CAL_SUCCESS

Indicates final calibration status of all interfaces in the IO96:

'1' All EMIF instances within the IO96 have calibrated successfully.

'0' One or more EMIF instances in the IO96 have either failed to calibrate or have not completed calibration yet.

RO 0x0