AXI Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes

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ID 815304
Date 7/08/2024
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1. AXI Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes
1. AXI Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes x
1.1. AXI Streaming Intel® FPGA IP for PCI Express* for IP Core v3.0.0 1.2. AXI Streaming Intel® FPGA IP for PCI Express* IP Core v2.0.0 1.3. AXI Streaming Intel® FPGA IP for PCI Express* IP Core v1.0.0
1. AXI Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes

1.2. AXI Streaming Intel® FPGA IP for PCI Express* IP Core v2.0.0

AXI Streaming Intel® FPGA IP for PCI Express* IP Core v2.0.0

Table 5.  v2.0.0 2024.04.01
Quartus® Prime Version Description Impact
24.1 Minor bug fixes have been implemented. The AXI Streaming Intel® FPGA IP for PCI Express* requires an automatic upgrade flow in Quartus® Prime when you use the 24.1 AXI Streaming Intel® FPGA IP in your design.
The IP version numbers have been changed. The 24.1 IP version numbers are:

2.0.0 (P-Tile)

2.0.0 (F-Tile)

2.0.0 (R-Tile)
Table 6.  AXI Streaming Intel® FPGA IP for PCI Express* IP Support Matrix for P-Tile in Quartus® Prime v24.1EP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = Simulation, C = Compilation, T = Timing, H = Hardware, N/A = Configuration not supported.
Configuration PCIe* IP Support Design Example Support
EP RP BP EP RP BP

Gen 4 x16

 S C T H N/A N/A S C T H N/A N/A

Gen4 x8/x8

 S C T H N/A N/A N/A N/A N/A

Gen 3 x16

 S C T H N/A N/A N/A N/A N/A

Gen3 x8/x8

 S C T H N/A N/A N/A N/A N/A
Table 7.  AXI Streaming Intel® FPGA IP for PCI Express* IP Support Matrix for F-Tile in Quartus® Prime v24.1EP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = Simulation, C = Compilation, T = Timing, H = Hardware, N/A = Configuration not supported.
Configuration PCIe* IP Support Design Example Support
EP RP BP EP RP BP

Gen 4 x16

 S C T H N/A N/A N/A N/A N/A

Gen4 x8/x8

 S C T H N/A N/A N/A N/A N/A

Gen 3 x16

 S C T H N/A N/A N/A N/A N/A

Gen3 x8/x8

 S C T H N/A N/A N/A N/A N/A
Table 8.  AXI Streaming Intel® FPGA IP for PCI Express* IP Support Matrix for R-Tile in Quartus® Prime v24.1EP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = Simulation, C = Compilation, T = Timing, H = Hardware, N/A = Configuration not supported.
Configuration PCIe* IP Support Design Example Support
EP RP BP EP RP BP

Gen 5 x16

 S C T H N/A N/A S C T H N/A N/A

Gen5 x8/x8

 S C T H N/A N/A N/A N/A N/A

Gen 4 x16

 S C T H N/A N/A N/A N/A N/A

Gen4 x8/x8

 S C T H N/A N/A N/A N/A N/A

Gen 3 x16

 S C T H N/A N/A N/A N/A N/A

Gen3 x8/x8

 S C T H N/A N/A N/A N/A N/A
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