AXI Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes

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Date 7/08/2024
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1. AXI Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes
1. AXI Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes x
1.1. AXI Streaming Intel® FPGA IP for PCI Express* for IP Core v3.0.0 1.2. AXI Streaming Intel® FPGA IP for PCI Express* IP Core v2.0.0 1.3. AXI Streaming Intel® FPGA IP for PCI Express* IP Core v1.0.0
1. AXI Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes

1.1. AXI Streaming Intel® FPGA IP for PCI Express* for IP Core v3.0.0

AXI Streaming Intel® FPGA IP for PCI Express* IP Core v3.0.0

Table 1.  v3.0.0 2024.07.08
Quartus® Prime Version Description Impact
24.2 Added support for the Performance design example The Performance design example can be generated in the IP Parameter Editor targeting devices with P-Tile, F-Tile, or R-Tile.
Added support for PCI Express configurations for the PIO, SRIOV, and Performance design examples. The PIO, SRIOV, and Performance design example support has been extended. Hence, these design examples may be generated with various configurations ranging from Gen3 1x4 up to Gen5 1x16.
Enabled Root Port mode. Devices with P-Tile, F-Tile, or R-Tile can now be generated with Root Port mode.
Table 2.  AXI Streaming Intel® FPGA IP for PCI Express* IP Support Matrix for P-Tile in Quartus® Prime v24.2EP = Endpoint, RP = Root Port, BP = TL Bypass. Support level keys: S = Simulation, C = Compilation, T = Timing, H = Hardware, N/A = Configuration not supported.
Configuration PCIe* IP Support Design Example Support (EP Mode Only)
EP RP BP PIO SRIOV Performance
Gen5 1x16 N/A N/A N/A N/A N/A N/A
Gen5 2x8 N/A N/A N/A N/A N/A N/A
Gen5 4x4 N/A N/A N/A N/A N/A N/A
Gen4 1x16 S C T H S C T H N/A S C T H S C T H S C T H
Gen4 2x8 S C T H N/A N/A S C T H S C T H S C T H
Gen4 1x8 S C T H N/A N/A S C T H S C T H S C T H
Gen4 4x4 S C T H S C T H N/A C T H C T H C T H
Gen4 2x4 S C T H S C T H N/A C T H C T H C T H
Gen4 1x4 S C T H S C T H N/A C T H C T H C T H
Gen3 x16 S C T H S C T H N/A S C T H S C T H S C T H
Gen3 2x8 S C T H N/A N/A S C T H S C T H S C T H
Gen3 1x8 S C T H N/A N/A S C T H S C T H S C T H
Gen3 4x4 S C T H S C T H N/A C T H C T H C T H
Gen3 2x4 S C T H S C T H N/A C T H C T H C T H
Gen3 1x4 S C T H S C T H N/A C T H C T H C T H
Table 3.  AXI Streaming Intel® FPGA IP for PCI Express* IP Support Matrix for F-Tile in Quartus® Prime v24.2EP = Endpoint, RP = Root Port, BP = TL Bypass. Support level keys: S = Simulation, C = Compilation, T = Timing, H = Hardware, N/A = Configuration not supported.
Configuration PCIe* IP Support Design Example Support (EP Mode Only)
EP RP BP PIO SRIOV Performance
Gen5 1x16 N/A N/A N/A N/A N/A N/A
Gen5 2x8 N/A N/A N/A N/A N/A N/A
Gen5 4x4 N/A N/A N/A N/A N/A N/A
Gen4 1x16 S C T H S C T H N/A S C T H S C T H S C T H
Gen4 2x8 S C T H N/A N/A S C T H S C T H S C T H
Gen4 1x8 S C T H S C T H N/A S C T H S C T H S C T H
Gen4 4x4 S C T H S C T H N/A C T H C T H C T H
Gen4 2x4 S C T H S C T H N/A C T H C T H C T H
Gen4 1x4 S C T H S C T H N/A C T H C T H C T H
Gen3 x16 S C T H S C T H N/A S C T H S C T H S C T H
Gen3 2x8 S C T H N/A N/A S C T H S C T H S C T H
Gen3 1x8 S C T H S C T H N/A S C T H S C T H S C T H
Gen3 4x4 S C T H S C T H N/A C T H C T H C T H
Gen3 2x4 S C T H S C T H N/A C T H C T H C T H
Gen3 1x4 S C T H S C T H N/A C T H C T H C T H
Table 4.  AXI Streaming Intel® FPGA IP for PCI Express* IP Support Matrix for R-Tile in Quartus® Prime v24.2EP = Endpoint, RP = Root Port, BP = TL Bypass. Support level keys: S = Simulation, C = Compilation, T = Timing, H = Hardware, N/A = Configuration not supported.
Configuration PCIe* IP Support Design Example Support (EP Mode Only)
EP RP BP PIO SRIOV Performance
Gen5 1x16 S C T H S C T H N/A S C T H S C T H S C T H
Gen5 2x8 S C T H S C T H N/A S C T H S C T H S C T H
Gen5 1x8 S C T H S C T H N/A S C T H S C T H S C T H
Gen5 4x4 S C T H N/A N/A C T H C T H C T H
Gen4 1x16 S C T H S C T H N/A S C T H S C T H S C T H
Gen4 2x8 S C T H N/A N/A S C T H S C T H S C T H
Gen4 1x8 S C T H S C T H N/A S C T H S C T H S C T H
Gen4 4x4 S C T H S C T H N/A C T H C T H C T H
Gen4 2x4 S C T H S C T H N/A C T H C T H C T H
Gen4 1x4 S C T H S C T H N/A C T H C T H C T H
Gen3 x16 S C T H S C T H N/A S C T H S C T H S C T H
Gen3 2x8 S C T H N/A N/A S C T H S C T H S C T H
Gen3 1x8 S C T H S C T H N/A S C T H S C T H S C T H
Gen3 4x4 S C T H S C T H N/A C T H C T H C T H
Gen3 2x4 S C T H S C T H N/A C T H C T H C T H
Gen3 1x4 S C T H S C T H N/A C T H C T H C T H
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