GTS JESD204C Intel® FPGA IP Design Example User Guide

ID 813978
Date 7/12/2024
Public

3.1.1. JTAG to Avalon® Master Bridge

The JTAG to Avalon® Master Bridge provides a connection between the host system to access the memory-mapped GTS JESD204C IP and the peripheral IP control and status registers through the JTAG interface.

Figure 6. System with a JTAG to Avalon® Master Bridge Core
Note: System clock must be at least 2X faster than the JTAG clock. The system clock is mgmt_clk (100MHz) in this design example.