GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Error Handling 3.5. Link Debugging Sequence
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

3.4. Error Handling

The GTS Serial Lite IV IP detects error conditions and the behaviors in response to these error conditions.

Table 9.  Error Condition BehaviorIn this table, N represents the number of lanes.
Signal Width Location Direction Clock Domain Error Indication
tx_error 5 Top-level signal Output tx_core_clkout Not used.
rx_error

(N*2)+3

Top-level signal Output rx_core_clkout

When asserted, indicates an error condition on the RX datapath.

  • [(N*2+2):N+3] = Indicates PCS error for a specific lane.
  • [N+2] = Indicates alignment error. Re-initialize lane alignment if this bit is asserted.
  • [N+1]= Indicates data is forwarded to the user logic when user logic is not ready.
  • [N] = Indicates loss of alignment.
  • [(N-1):0] = Indicates the data contains CRC error.

tx_adaptation_fifo_full

1

Top-level TX DCFIFO signal

 Output TX user clock This vector indicates the write domain TX buffer is full and cannot accept data.

rx_adaptation_fifo_full

1

Top-level RX DCFIFO signal

 Output RX user clock This vector indicates the write domain RX buffer is full and cannot accept data.

readfull

1

Top-level RX DCFIFO signal

 Output RX user clock This vector indicates the read domain buffer is full and cannot accept data.
Level Two Title