ID
813973
Date
4/01/2024
Public
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
Updated for: |
---|
Intel® Quartus® Prime Design Suite 24.1 |
IP Version 3.0.0 |
This document provides features, usage guidelines, and functional description of the GTS Serial Lite IV Intel® FPGA IP design examples using transceivers in Agilex™ 5 devices.
Intended Audience
This document is intended for the following users:
- Design architects to make IP selection during system level design planning phase.
- Hardware designers when integrating the IP into their system level design.
- Validation engineers during system level simulation and hardware validation phase.
Related Documents
For other documents related to the GTS Serial Lite IV Intel® FPGA IP, refer to the related information.
Acronyms and Glossary
Acronym | Expansion |
---|---|
CW | Control Word |
RS-FEC | Reed-Solomon Forward Error Correction |
PMA | Physical Medium Attachment |
TX | Transmitter |
RX | Receiver |
PAM4 | Pulse-Amplitude Modulation 4-Level |
NRZ | Non-return-to-zero |
PCS | Physical Coding Sublayer |
MII | Media Independent Interface |
XGMII | 10 Gigabit Media Independent Interface |