Variable Precision DSP Blocks User Guide: Agilex™ 5 FPGAs and SoCs

ID 813968
Date 9/20/2024
Public
Document Table of Contents

2.3.3. Pipeline Registers for Tensor Mode

There are three columns of pipeline registers for tensor mode. These pipeline registers are not bypassable. The first and second pipeline registers are required for Tensor floating-point and tensor fixed-point modes, whereas the third pipeline register is required for tensor floating-point and tensor accumulation mode.