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Ixiasoft
2.4. Simulation
The simulation test case performs the following steps:
- Instantiates Triple-Speed Ethernet Intel® FPGA IP.
- Starts up the design example with an operating speed of 1G.
- Waits for RX clock and RX alignment to settle.
- Sends and receives 5 valid packets on 1G speed.
- Completes the simulation and displays End of Simulation.
When the testbench starts, it waits for rx_ready to go high. It then sends 5 packets to the TX Avalon® streaming interface and waits for those 5 packets to be received on the RX Avalon® streaming interface.