1.1. Directory Structure
The Triple-Speed Ethernet Intel® FPGA IP design example file directories contain the following generated files for the 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS:
- The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design.
- The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
- The compilation-only design example is located in <design_example_dir>/compilation_test_design.
- The compilation test and hardware test designs use files in <design_example_dir>/ex_tse/common.
Figure 2. Directory Structure for the Design Example
Directory/File | Description |
---|---|
Testbench and Simulation Files | |
<design_example_dir>/example_testbench/basic_avl_tb_top_2xtbi_pma_ag.sv | Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. |
<design_example_dir>/example_testbench/ basic_avl_tb_top_2xtbi_pma_ag_msim.sv | Top-level testbench file for QuestaSim* simulation. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. |
<design_example_dir>/example_testbench/ basic_avl_tb_top_2xtbi_pma_ag_nc.sv | Top-level testbench file for Xcelium* simulation. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. |
Testbench Scripts | |
<design_example_dir>/example_testbench/ run_vsim_2xtbi_pma.do | The QuestaSim* script to run the testbench. |
<design_example_dir>/example_testbench/run_vcs_2xtbi_pma.sh | The Synopsys* VCS script to run the testbench. |
<design_example_dir>/example_testbench/run_vcsmx_2xtbi_pma.sh | The Synopsys* VCS MX script to run the testbench |
<design_example_dir>/example_testbench/run_xcelium_2xtbi_pma.sh | The Xcelium* script to run the testbench. |
Directory/File | Description |
---|---|
<design_example_dir>/hardware_test_design/ intel_eth_tse_hw.qpf |
Quartus® Prime project file. |
<design_example_dir>/hardware_test_design/ intel_eth_tse_hw.qsf |
Quartus® Prime project settings file. |
<design_example_dir>/hardware_test_design/intel_eth_tse_hw.sdc |
Synopsys* Design Constraints files. You can copy and modify these files for your own design. |
<design_example_dir>/hardware_test_design/ intel_eth_tse_hw.v |
Top-level Verilog HDL design example file. |
<design_example_dir>/hardware_test_design/common/ |
Hardware design example support files. |