Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813741
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Agilex™ 5 Device Design Guidelines 2. System Specification 3. Device Selection 4. Design Entry 5. Board and Software consideration 6. Design Implementation, Analysis, Optimization and Verification 7. Debugging
1. Introduction to Agilex™ 5 Device Design Guidelines x
1.1. Introduction to Agilex™ 5 Device Design Guide Revision History
2. System Specification x
2.1. Design Specification 2.2. Install Quartus® Prime Software 2.3. IP selection 2.4. Simulation 2.5. Preparing for Design Entry 2.6. I/O Summary 2.7. Using SDM in your devices 2.8. System Specification Revision History
2.3. IP selection x
2.3.1. IP cores 2.3.2. HPS IP
2.3.1. IP cores x
2.3.1.1. Interface Protocol IP cores
2.4. Simulation x
2.4.1. RTL Simulation 2.4.2. Simics® Simulator
2.5. Preparing for Design Entry x
2.5.1. Coding Styles and Design Recommendation 2.5.2. Platform Designer
3. Device Selection x
3.1. Device Variant 3.2. Device Selection Revision History
3.1. Device Variant x
3.1.1. Speed Grade and Package 3.1.2. Power option 3.1.3. Device Migration within Agilex™ 5 3.1.4. PLL 3.1.5. Logic element, Embedded memory, and DSP 3.1.6. I/O and LVDS SERDES 3.1.7. MIPI D-DPHY 3.1.8. Transceiver 3.1.9. Hard Processor System
4. Design Entry x
4.1. Design entry for FPGA 4.2. Design entry for Nios® V 4.3. Design entry for HPS 4.4. Design Entry Revision History
4.1. Design entry for FPGA x
4.1.1. Configuration Consideration 4.1.2. I/O and LVDS SERDES 4.1.3. PLL and Clock Planning 4.1.4. EMIF 4.1.5. Transceiver Planning 4.1.6. Sensors 4.1.7. MIPI D-PHY
4.1.1. Configuration Consideration x
4.1.1.1. Partial Reconfiguration 4.1.1.2. SEU
4.1.2. I/O and LVDS SERDES x
4.1.2.1. Making FPGA Pin Assignments Checklist 4.1.2.2. Early Pin Planning and I/O Assignment Analysis for the FPGA Device 4.1.2.3. Agilex™ 5 I/O Features and Pin Connections
4.1.2.3. Agilex™ 5 I/O Features and Pin Connections x
4.1.2.3.1. I/O Signaling Type 4.1.2.3.2. Selectable Standards and Flexible I/O Banks 4.1.2.3.3. Agilex™ 5 Dual-Purpose and Special Pin Connections 4.1.2.3.4. Agilex™ 5 I/O Features
4.1.3. PLL and Clock Planning x
4.1.3.1. Clock and PLL Selection 4.1.3.2. PLL Feature Guidelines 4.1.3.3. Clock Feedback Mode 4.1.3.4. Clock Outputs 4.1.3.5. Clock Control Features
4.1.6. Sensors x
4.1.6.1. Voltage sensor 4.1.6.2. Temperature Sensor and Temperature Diode
4.3. Design entry for HPS x
4.3.1. Simics® Simulator 4.3.2. HPS IP Instantiation in Quartus® Prime
5. Board and Software consideration x
5.1. Early Board Planning 5.2. Boundary Scan for FPGA and HPS 5.3. Pin Connection Considerations for Board Design 5.4. Planning for Device Configuration 5.5. Board and Software Consideration Revision History
5.1. Early Board Planning x
5.1.1. Power - SmartVID or Fix Voltage 5.1.2. Thermal Management and Design
5.1.1. Power - SmartVID or Fix Voltage x
5.1.1.1. Intel® FPGA Power and Thermal Calculator 5.1.1.2. Power-Up and Power-Down Sequencing
5.3. Pin Connection Considerations for Board Design x
5.3.1. Board-Related Quartus® Prime Settings 5.3.2. Signal Integrity Considerations 5.3.3. Board-Level Simulation and Advanced I/O Timing Analysis
5.3.1. Board-Related Quartus® Prime Settings x
5.3.1.1. Unused Pins
5.3.2. Signal Integrity Considerations x
5.3.2.1. High-Speed Board Design 5.3.2.2. Simultaneous Switching Noise 5.3.2.3. I/O Termination
5.4. Planning for Device Configuration x
5.4.1. Device Power Cycling and Reconfiguration 5.4.2. Configuration Scheme Selection 5.4.3. Configuration Features 5.4.4. Quartus® Prime Configuration Settings 5.4.5. Configuration Pin Connections 5.4.6. JTAG Pins 5.4.7. MSEL Configuration Mode Pins 5.4.8. Other Configuration Pins
5.4.2. Configuration Scheme Selection x
5.4.2.1. Serial Configuration Devices 5.4.2.2. Intel® FPGA Download Cable II
5.4.4. Quartus® Prime Configuration Settings x
5.4.4.1. Optional Configuration Pins 5.4.4.2. Dual Purpose Configuration Pins
5.4.5. Configuration Pin Connections x
5.4.5.1. Configuration Pin Voltage Level 5.4.5.2. Clock Trace Signal Integrity
5.4.6. JTAG Pins x
5.4.6.1. JTAG Pin Connections 5.4.6.2. JTAG Signal Buffering 5.4.6.3. Download Cable Operating Voltage
6. Design Implementation, Analysis, Optimization and Verification x
6.1. Synthesis Tool 6.2. Device Resource Reports 6.3. Quartus® Prime Message 6.4. Design Assistant Design Rule Checking 6.5. Timing Constraints and Analysis 6.6. Area and Timing Optimization 6.7. Preserving Performance and Reducing Compilation Time 6.8. Designing with Hyperflex® 6.9. Simulation 6.10. Power Analysis 6.11. Design Implementation, Analysis, Optimization and Verification Revision History
6.5. Timing Constraints and Analysis x
6.5.1. Recommended Timing Optimization and Analysis Assignments 6.5.2. SDC-on-RTL and Post-Synthesis Static Timing Analysis
7. Debugging x
7.1. On-Chip Debug Overview 7.2. On-Chip Debugging Tools 7.3. Debugging Revision History
1. Introduction to Agilex™ 5 Device Design Guidelines
2. System Specification
3. Device Selection
4. Design Entry
5. Board and Software consideration
6. Design Implementation, Analysis, Optimization and Verification
7. Debugging

5.4.5.1. Configuration Pin Voltage Level

Table 55.  Configuration Pin Voltage Level Checklist
Number Done? Checklist Item
1   Ensure VCCIO_SDM and VCCIO of the configuration pins match the voltage level of the external devices used for configuration.

Configuration pins from the Agilex™ 5 device connect to external devices, for example the Quad SPI flash configuration device, or Avalon® -ST host. The voltage level of the configuration pins need to match the voltage level of the devices connected to them. The JTAG and SDM I/Os used as configuration pins are powered by the VCCIO_SDM supply. For Avalon® -ST ×16 configuration schemes, the AVST_CLK, AVST_READY, AVST_VALID, and AVST_DATA pins are powered by the VCCIO of the I/O bank in which the pins reside in.

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