Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813669
Date 10/07/2024
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Document Table of Contents
Document Table of Contents x
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs A. Ethernet Frame Format B. Simulation Parameters
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices x
1.1. Release Information 1.2. Device Family Support 1.3. Features 1.4. 10/100/1000 Ethernet MAC Versus Small MAC 1.5. High-Level Block Diagrams 1.6. Performance and Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Generation Output 2.5. Simulating Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.4. IP Core Generation Output x
2.4.1. Design Constraint File
3. Parameter Settings x
3.1. Core Configuration 3.2. Ethernet MAC Options 3.3. FIFO Options 3.4. PCS/Transceiver Options 3.5. Analog Parameter Settings
4. Functional Description x
4.1. 10/100/1000 Ethernet MAC 4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA (GTS)
4.1. 10/100/1000 Ethernet MAC x
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Reset 4.1.11. PHY Management (MDIO) 4.1.12. Connecting MAC to External PHYs
4.1.3. MAC Transmit Datapath x
4.1.3.1. IP Payload Re-alignment 4.1.3.2. Address Insertion 4.1.3.3. Frame Payload Padding 4.1.3.4. CRC-32 Generation 4.1.3.5. Interpacket Gap Insertion 4.1.3.6. Collision Detection in Half-Duplex Mode
4.1.4. MAC Receive Datapath x
4.1.4.1. Preamble Processing 4.1.4.2. Collision Detection in Half-Duplex Mode 4.1.4.3. Address Checking 4.1.4.4. Frame Type Validation 4.1.4.5. Payload Pad Removal 4.1.4.6. CRC Checking 4.1.4.7. Length Checking 4.1.4.8. Frame Writing 4.1.4.9. IP Payload Alignment
4.1.4.3. Address Checking x
4.1.4.3.1. Unicast Address Checking 4.1.4.3.2. Multicast Address Resolution
4.1.6. FIFO Buffer Thresholds x
4.1.6.1. Receive Thresholds 4.1.6.2. Transmit Thresholds 4.1.6.3. Transmit FIFO Buffer Underflow
4.1.7. Congestion and Flow Control x
4.1.7.1. Remote Device Congestion 4.1.7.2. Receive FIFO Buffer and Local Device Congestion
4.1.8. Magic Packets x
4.1.8.1. Sleep Mode 4.1.8.2. Magic Packet Detection
4.1.11. PHY Management (MDIO) x
4.1.11.1. MDIO Connection 4.1.11.2. MDIO Frame Format
4.1.12. Connecting MAC to External PHYs x
4.1.12.1. Gigabit Ethernet 4.1.12.2. Programmable 10/100 Ethernet 4.1.12.3. Programmable 10/100/1000 Ethernet Operation
4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA (GTS) x
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. 1000BASE-X/SGMII PCS Reset
4.2.2. Transmit Operation x
4.2.2.1. Frame Encapsulation 4.2.2.2. 8b/10b Encoding
4.2.3. Receive Operation x
4.2.3.1. Comma Detection 4.2.3.2. 8b/10b Decoding 4.2.3.3. Frame De-encapsulation 4.2.3.4. Synchronization 4.2.3.5. Carrier Sense 4.2.3.6. Collision Detection
4.2.6. SGMII Converter x
4.2.6.1. Transmit 4.2.6.2. Receive
4.2.7. Auto-Negotiation x
4.2.7.1. 1000BASE-X Auto-Negotiation 4.2.7.2. SGMII Auto-Negotiation
5. Configuration Register Space x
5.1. MAC Configuration Register Space 5.2. PCS Configuration Register Space 5.3. Register Initialization
5.1. MAC Configuration Register Space x
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7)
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) x
5.1.1.1. Command_Config Register (Dword Offset 0x02)
5.2. PCS Configuration Register Space x
5.2.1. Control Register (Word Offset 0x00) 5.2.2. Status Register (Word Offset 0x01) 5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) 5.2.4. An_Expansion Register (Word Offset 0x06) 5.2.5. If_Mode Register (Word Offset 0x14)
5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) x
5.2.3.1. 1000BASE-X 5.2.3.2. SGMII MAC Mode Auto Negotiation 5.2.3.3. SGMII PHY Mode Auto Negotiation
5.3. Register Initialization x
5.3.1. Triple-Speed Ethernet System with MII/GMII or RGMII 5.3.2. Triple-Speed Ethernet System with SGMII 5.3.3. Triple-Speed Ethernet System with 1000BASE-X Interface
6. Interface Signals x
6.1. Interface Signals 6.2. Timing
6.1. Interface Signals x
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals 6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.6. 1000BASE-X/SGMII PCS Signals 6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.8. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals 6.1.9. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals
6.1.1. 10/100/1000 Ethernet MAC Signals x
6.1.1.1. Clock and Reset Signals 6.1.1.2. Clock Enabler Signals 6.1.1.3. MAC Control Interface Signals 6.1.1.4. MAC Status Signals 6.1.1.5. MAC Receive Interface Signals 6.1.1.6. MAC Transmit Interface Signals 6.1.1.7. Pause and Magic Packet Signals 6.1.1.8. MII/GMII/RGMII Signals 6.1.1.9. PHY Management Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals x
6.1.2.1. Multiport MAC Clock and Reset Signals 6.1.2.2. Multiport MAC Receive Interface Signals 6.1.2.3. Multiport MAC Transmit Interface Signals 6.1.2.4. Multiport MAC Packet Classification Signals 6.1.2.5. Multiport MAC FIFO Status Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals x
6.1.3.1. TBI Interface Signals 6.1.3.2. Status LED Control Signals 6.1.3.3. SERDES Control Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals x
6.1.4.1. GMII Clock Signals 6.1.4.2. GTS Transceiver Direct PHY Signals 6.1.4.3. GTS Reset Sequencer Signals 6.1.4.4. PMA Reconfiguration Interface Signals
6.1.6. 1000BASE-X/SGMII PCS Signals x
6.1.6.1. PCS Control Interface Signals 6.1.6.2. PCS Reset Signals 6.1.6.3. MII/GMII Clocks and Clock Enablers 6.1.6.4. GMII 6.1.6.5. MII 6.1.6.6. SGMII Status Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals x
6.1.7.1. Clock Enablers 6.1.7.2. PCS Reset Signals 6.1.7.3. TBI Interface Signals
6.1.8. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals x
6.1.8.1. 1.25 Gbps LVDS Serial Interface
6.2. Timing x
6.2.1. Avalon Streaming Receive Interface 6.2.2. Avalon Streaming Transmit Interface 6.2.3. GMII Transmit 6.2.4. GMII Receive 6.2.5. RGMII Transmit 6.2.6. RGMII Receive 6.2.7. MII Transmit 6.2.8. MII Receive
7. Design Considerations x
7.1. Exposed Ports in the New User Interface 7.2. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA (GTS)
8. Timing Constraints x
8.1. Creating Clock Constraints 8.2. Recommended Clock Frequency
9. Testbench x
9.1. Triple-Speed Ethernet Testbench Architecture 9.2. Testbench Components 9.3. Testbench Verification 9.4. Testbench Configuration 9.5. Test Flow 9.6. Simulation Model
9.6. Simulation Model x
9.6.1. Generate the Simulation Model 9.6.2. Simulate the IP 9.6.3. Simulation Model Files
A. Ethernet Frame Format x
A.1. Basic Frame Format A.2. VLAN and Stacked VLAN Frame Format A.3. Pause Frame Format
A.3. Pause Frame Format x
A.3.1. Pause Frame Generation
B. Simulation Parameters x
B.1. Functionality Configuration Parameters B.2. Test Configuration Parameters
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters

5.1. MAC Configuration Register Space

Use the registers to configure the different aspects of the MAC function and retrieve its status and statistics counters.
In multiport MACs, a contiguous register space is allocated for all ports and accessed via the Avalon® memory-mapped control interface. For example, if the register space base address for the first port is 0x00, the base address for the next port is 0x100 and so forth. The registers that are shared among the instances occupy the register space of the first port. Updating these registers in the register space of other ports has no effect on the configuration.
Note: If you select 10/100/1000Mb Ethernet MAC variant and deselect Use clock enable for MAC in the parameter editor of the Triple-Speed Ethernet Intel® FPGA IP, the CSR access latency will be dependent on the datapath clock frequency.
Table 24.  Overview of MAC Register Space
Dword Offset Section Description
0x00 – 0x17 Base Configuration Base registers to configure the MAC function. At the minimum, you must configure the following functions:
  • Primary MAC address (mac_0/mac_1)
  • Enable transmit and receive paths (TX_ENA and RX_ENA bits in the command_config register)

The following registers are shared among all instances of a multiport MAC:

  • rev
  • scratch
  • frm_length
  • pause_quant
  • mdio_addr0 and mdio_addr1
  • tx_ipg_length
0x18 – 0x38 Statistics Counters Counters collecting traffic statistics.
0x3A Transmit Command Transmit and receive datapaths control register.
0x3B Receive Command
0x3C – 0x3E Extended Statistics Counters Upper 32 bits of selected statistics counters. These registers are used if you turn on the option to use extended statistics counters.
0x3F Reserved 8 Unused.
0x40 – 0x7F Multicast Hash Table 64-entry write-only hash table to resolve multicast addresses. Only bit 0 in each entry is significant. When you write a 1 to a dword offset in the hash table, the MAC accepts all multicast MAC addresses that hash to the value of the address (bits 5:0). Otherwise, the MAC rejects the multicast address. This table is cleared during reset.
0x80 – 0x9F MDIO Space 0 or

PCS Function Configuration

MDIO Space 0 and MDIO Space 1 map to registers 0 to 31 of the PHY devices whose addresses are configured in the mdio_addr0 and mdio_addr1 registers respectively. For example, register 0 of PHY device 0 maps to dword offset 0x80, register 1 maps to dword offset 0x81 and so forth.

Reading or writing to MDIO Space 0 or MDIO Space 1 immediately triggers a corresponding MDIO transaction to read or write the PHY register. Only bits [15:0] of each register are significant. Write 0 to bits [31:16] and ignore them on reads.

If your variation does not include the PCS function, you can use MDIO Space 0 and MDIO Space 1 to map to two PHY devices.

If your MAC variation includes the PCS function, the PCS function is always device 0 and its configuration registers occupy MDIO Space 0. You can use MDIO Space 1 to map to a PHY device.

0xA0 – 0xBF

MDIO Space 1
0xC0 – 0xC7 Supplementary Address Supplementary unicast addresses.
0xC8 – 0xCF Reserved 8 Unused.
0xD0 – 0xD6 Reserved 8 Unused.
0xD7 – 0xE0 Reserved 8 Unused.
0xE1 – 0xE3 Reserved 8 Unused.

Section Content
Base Configuration Registers (Dword Offset 0x00 – 0x17)
Statistics Counters (Dword Offset 0x18 – 0x38)
Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
Supplementary Address (Dword Offset 0xC0 – 0xC7)

8 Altera recommends that you set all bits in the reserved registers to 0 and ignore them on reads.
Level Two Title