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4.6.1. Launching and Setting Up the Fault Injection Debugger
4.6.2. Configuring Your Device using a Software Object File (.sof)
4.6.3. Constraining Regions for Fault Injection
4.6.4. Injecting Errors to Predefined Safe Locations
4.6.5. Blowing Fuse Bit to Enable Injecting All Error Types
4.6.6. Injecting Errors to Random Locations
4.6.7. Injecting Errors to Specific Locations
4.6.8. Injecting Double Adjacent Errors
4.6.9. Injecting SDM ECC Errors
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2.5.1. Hierarchy Tagging
The Quartus® Prime hierarchy tagging feature allows you to improve your design's effective FIT rate by tagging only the logic that are critical to device operation.
You can define the system recovery procedure based on knowledge of logic impaired by SEU. This technique reduces downtime for the FPGA and the system in which the FPGA resides.
Other advantages of hierarchy tagging:
- Increases system stability by avoiding disruptive recovery procedures for inconsequential errors
- Allows diverse corrective actions for different design logic
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