F-Tile Triple-Speed Ethernet Intel FPGA IP Design Example User Guide

ID 781679
Date 6/26/2023

1.3. Simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench

Figure 5. Procedure to Simulate Example Testbench
Follow these steps to simulate the testbench:
  1. At the command prompt, navigate to the compilation_test_design folder in your example design:
    cd eth_tse_0_example_design/compilation_test_design
  2. Run the following command:
    quartus_tlg altera_eth_tse.qpf
  3. Navigate to the sim directory:
    cd eth_tse_0_example_design/ex_tse/sim/
  4. Run the IP setup simulation:
    ip-setup-simulation --quartus-project=../../compilation_test_design/altera_eth_tse.qpf
  5. Navigate to the testbench simulation directory:
    cd eth_tse_0_example_design/example_testbench/
  6. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
    Table 3.  Steps to Simulate the Testbench
    Simulator Instructions
    ModelSim* In the command line, type vsim -do run_vsim_2xtbi_pma.do. If you prefer to simulate without bringing up the ModelSim* GUI, type vsim -c -do run_vsim_2xtbi_pma.do.
    Synopsys* VCS* In the command line, type sh run_vcs_2xtbi_pma.sh.
    Xcelium* In the command line, type sh run_xcelium_2xtbi_pma.sh.
  7. Analyze the results. The successful testbench sends five packets, receives the same number of packets, and displays the following message:
End of Simulation - Break

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