F-Tile Triple-Speed Ethernet Intel FPGA IP Design Example User Guide

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ID 781679
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver 3. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver x
2.1. Features 2.2. Software Requirements 2.3. Functional Description 2.4. Simulation
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

2.1. Features

  • Generates the design example for Triple-Speed Ethernet MAC 2XTBI with Internal FIFO and PCS with PMA.
  • Generates traffic at the transmit path and validates received data through the F-Tile transceiver external loopback.
  • TX and RX serial loopback mode.
  • Supports only external loopback.
  • Supports only a single port.
  • Supports packet statistics report on both MAC transmitter and MAC receiver.
  • Basic packet checking capabilities of traffic monitor.
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