F-Tile Triple-Speed Ethernet Intel FPGA IP Design Example User Guide

ID 781679
Date 6/26/2023

2.1. Features

  • Generates the design example for Triple-Speed Ethernet MAC 2XTBI with Internal FIFO and PCS with PMA.
  • Generates traffic at the transmit path and validates received data through the F-Tile transceiver external loopback.
  • TX and RX serial loopback mode.
  • Supports only external loopback.
  • Supports only a single port.
  • Supports packet statistics report on both MAC transmitter and MAC receiver.
  • Basic packet checking capabilities of traffic monitor.

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