External Memory Interfaces Agilex™ 7 M-Series FPGA IP Core Release Notes

ID 772635
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

1.1. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.1.0

Table 1.  v6.1.0 2024.04.01
Description Impact
Verified in the Quartus® Prime software v24.1. Provides external memory interface IP for DDR4, DDR5, and LPDDR5 external memory for Agilex™ 7 M-Series devices.
Added support for the Performance Monitor (PMON) FPGA IP. Provides a synthesizable IP for measuring performance on an interface.
Added support for the Test Engine FPGA IP. Provides a software-driven programmable AXI traffic generator.

Known Issues in this Version

For a list of known issues affecting this release of the External Memory Interfaces Agilex™ 7 M-Series FPGA IP, follow this link to the: FPGA Knowledge Base.