Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 4/01/2024
Public
Document Table of Contents

GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications

Table 23.  GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) Internal VREF (V) VTT (V)
Min Typ Max Min Typ Max Min Typ Max
SSTL-12 1.14 1.2 1.26 0.49 × VCCIO_PIO 0.5 × VCCIO_PIO 0.51 × VCCIO_PIO 0.45 × VCCIO_PIO 0.5 × VCCIO_PIO 0.55 × VCCIO_PIO
HSTL-12 1.14 1.2 1.26 0.47 × VCCIO_PIO 0.5 × VCCIO_PIO 0.53 × VCCIO_PIO 0.45 × VCCIO_PIO 0.5 × VCCIO_PIO 0.55 × VCCIO_PIO
HSUL-1238 1.14 1.2 1.26 0.49 × VCCIO_PIO 0.5 × VCCIO_PIO 0.51 × VCCIO_PIO 0.45 × VCCIO_PIO 0.5 × VCCIO_PIO 0.55 × VCCIO_PIO
POD1239 1.164 1.2 1.236 0.69 × VCCIO_PIO 0.7 × VCCIO_PIO 0.71 × VCCIO_PIO VCCIO_PIO
POD1139 1.067 1.1 1.133 0.69 × VCCIO_PIO 0.7 × VCCIO_PIO 0.71 × VCCIO_PIO VCCIO_PIO
38 Usage of receiver termination is optional.
39 You may supply the VCCIO_PIO voltage rail of a sub-bank with a ±5% voltage tolerance only if the entire GPIO-B sub-bank is operating in any of LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard, PHYLITE mode, or GPIO mode. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.