FPGA AI Suite: IP Reference Manual

ID 768974
Date 9/06/2024
Public
Document Table of Contents

5.5. Performance Registers

Hardware counters are provided to measure how many clock cycles that the IP is active. A job is considered active after the first word of its descriptor is read from the descriptor queue. A job is considered finished just before the done interrupt is raised and the completion count is updated.

The IP and supporting host form an elastic pipeline in which multiple jobs can be in flight. The IP tracks both the overall latency (for example, the length of time required to process 100 jobs) as well as the average latency for each of those jobs. The hardware tracks the total latency of every job but knowing the total number of jobs software can compute the average.

64-bit counters mitigate against overflow. There is no synchronization between reading the lower or upper 32 bits of a counter, therefore the software should not read the counters while the IP is active.

Table 17.  Performance Registers

Register

Offset

Attribute

Description

Total clocks active

(lower 32 bits)

0x000

RO

On each clock cycle, if any IP job is active, increment the counter by 1.

Total clocks active

(upper 32 bits)

0x004

RO

Same as above.

Total clocks for all jobs

(lower 32 bits)

0x008

RO

On each clock cycle, if there are N IP jobs active, increment the counter by N.

Total clocks for all jobs

(upper 32 bits)

0x00C

RO

Same as above.