AN 988: Using the Board-Aware Flow: in the Intel® Quartus® Prime Pro Edition Software

ID 757339
Date 1/09/2023
Public

2.2. Download and Extract Supporting Files

  1. Download and extract the Board-Aware Design Example Supporting Files to a directory on your computer. Do not use spaces in the directory path name.
  2. View the extracted tutorial design files and directory structure. board_aware_example_agilex.zip contains the following files:
Table 1.  Supporting Design Example Files
File Description
pin_pio.tcl Tcl pin constraints file that contains appropriate pin assignments for the system. You can optionally load this file rather than manual entry.
pio_led.out.sdc Synopsys Design Constraints file that contains appropriate timing constraints for the completed design.
issp.ip Represents the In-System Sources and Probes Intel® FPGA IP in the design for use in debugging the design.
resetrelease.ip Represents the Reset Release Intel FPGA IP in the design. This IP outputs nINIT_DONE after finishing device initialization. User mode initialization can begin as soon as the nINIT_DONE signal asserts.