Symmetric Cryptographic Intel® FPGA Hard IP Release Notes

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ID 722029
Date 4/03/2023
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1. Symmetric Cryptographic Intel FPGA Hard IP Release Notes
1. Symmetric Cryptographic Intel FPGA Hard IP Release Notes x
1.1. Symmetric Cryptographic Intel FPGA Hard IP v1.4.0 1.2. Symmetric Cryptographic Intel FPGA Hard IP v1.3.0 1.3. Symmetric Cryptographic Intel FPGA Hard IP v1.2.0 1.4. Symmetric Cryptographic Intel FPGA Hard IP v1.1.1 1.5. Symmetric Cryptographic Intel FPGA Hard IP v1.1.0 1.6. Symmetric Cryptographic Intel FPGA Hard IP v1.0.0 1.7. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
1. Symmetric Cryptographic Intel FPGA Hard IP Release Notes

1.5. Symmetric Cryptographic Intel FPGA Hard IP v1.1.0

Table 5.  v1.1.0 2022.03.28
Intel® Quartus® Prime Version Description Impact
22.1 Removed the 256-bit AXI-ST interface. You must regenerate the IP with the Intel® Quartus® Prime software version 22.1.
Frame-based interleaving has been validated. The 22.1 release does not support cycle-based mixed profile interleaving. —
Added minimum frame size restriction for the XTS profile.

When XTS profile interleaves with other profiles, the XTS minimum frame size is 241 bytes.

When using XTS profile only, no frame size restriction.
The XTS Protection parameter and cycle interleaving feature have not been fully validated. Do not select the XTS Protection parameter. Perform packet-to-packet switching when interleaving XTS profile with other profiles.
Added limited support for example design. The design example is only available for simulation using Synopsys VCS* and VCS* MX simulators.

The hardware support is not available in the 22.1 release.
Added the following simulator support for the Symmetric Cryptographic Intel FPGA Hard IP core:
  • Synopsys VCS* and VCS* MX
  • Cadence Xcelium*
  • Siemens QuestaSim*
  • Aldec Riviera-PRO*
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